1/* 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/bcm3380-clock.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/reset/bcm3380-reset.h> 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "brcm,bcm3380"; 14 15 aliases { 16 spi0 = &spi; 17 }; 18 19 cpus { 20 reg = <0x14e00000 0x4>; 21 #address-cells = <1>; 22 #size-cells = <0>; 23 u-boot,dm-pre-reloc; 24 25 cpu@0 { 26 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc"; 27 device_type = "cpu"; 28 reg = <0>; 29 u-boot,dm-pre-reloc; 30 }; 31 32 cpu@1 { 33 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc"; 34 device_type = "cpu"; 35 reg = <1>; 36 u-boot,dm-pre-reloc; 37 }; 38 }; 39 40 clocks { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 u-boot,dm-pre-reloc; 45 46 periph_osc: periph-osc { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <48000000>; 50 u-boot,dm-pre-reloc; 51 }; 52 53 periph_clk0: periph-clk@14e00004 { 54 compatible = "brcm,bcm6345-clk"; 55 reg = <0x14e00004 0x4>; 56 #clock-cells = <1>; 57 }; 58 59 periph_clk1: periph-clk@14e00008 { 60 compatible = "brcm,bcm6345-clk"; 61 reg = <0x14e00008 0x4>; 62 #clock-cells = <1>; 63 }; 64 }; 65 66 ubus { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 u-boot,dm-pre-reloc; 71 72 memory-controller@12000000 { 73 compatible = "brcm,bcm6328-mc"; 74 reg = <0x12000000 0x1000>; 75 u-boot,dm-pre-reloc; 76 }; 77 78 periph_rst0: reset-controller@14e0008c { 79 compatible = "brcm,bcm6345-reset"; 80 reg = <0x14e0008c 0x4>; 81 #reset-cells = <1>; 82 }; 83 84 periph_rst1: reset-controller@14e00090 { 85 compatible = "brcm,bcm6345-reset"; 86 reg = <0x14e00090 0x4>; 87 #reset-cells = <1>; 88 }; 89 90 pll_cntl: syscon@14e00094 { 91 compatible = "syscon"; 92 reg = <0x14e00094 0x4>; 93 }; 94 95 syscon-reboot { 96 compatible = "syscon-reboot"; 97 regmap = <&pll_cntl>; 98 offset = <0x0>; 99 mask = <0x1>; 100 }; 101 102 wdt: watchdog@14e000dc { 103 compatible = "brcm,bcm6345-wdt"; 104 reg = <0x14e000dc 0xc>; 105 106 clocks = <&periph_osc>; 107 }; 108 109 wdt-reboot { 110 compatible = "wdt-reboot"; 111 wdt = <&wdt>; 112 }; 113 114 gpio0: gpio-controller@14e00100 { 115 compatible = "brcm,bcm6345-gpio"; 116 reg = <0x14e00100 0x4>, <0x14e00108 0x4>; 117 gpio-controller; 118 #gpio-cells = <2>; 119 120 status = "disabled"; 121 }; 122 123 gpio1: gpio-controller@14e00104 { 124 compatible = "brcm,bcm6345-gpio"; 125 reg = <0x14e00104 0x4>, <0x14e0010c 0x4>; 126 gpio-controller; 127 #gpio-cells = <2>; 128 ngpios = <3>; 129 130 status = "disabled"; 131 }; 132 133 uart0: serial@14e00200 { 134 compatible = "brcm,bcm6345-uart"; 135 reg = <0x14e00200 0x18>; 136 clocks = <&periph_osc>; 137 138 status = "disabled"; 139 }; 140 141 uart1: serial@14e00220 { 142 compatible = "brcm,bcm6345-uart"; 143 reg = <0x14e00220 0x18>; 144 clocks = <&periph_osc>; 145 146 status = "disabled"; 147 }; 148 149 spi: spi@14e02000 { 150 compatible = "brcm,bcm6358-spi"; 151 reg = <0x14e02000 0x70c>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 clocks = <&periph_clk0 BCM3380_CLK0_SPI>; 155 resets = <&periph_rst0 BCM3380_RST0_SPI>; 156 spi-max-frequency = <25000000>; 157 num-cs = <6>; 158 159 status = "disabled"; 160 }; 161 162 leds: led-controller@14e00f00 { 163 compatible = "brcm,bcm6328-leds"; 164 reg = <0x14e00f00 0x1c>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 status = "disabled"; 169 }; 170 }; 171}; 172