1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Marek Vasut <marex@denx.de> 4 */ 5 6#include "skeleton.dtsi" 7 8/ { 9 compatible = "qca,ar934x"; 10 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "mips,mips74Kc"; 21 reg = <0>; 22 }; 23 }; 24 25 clocks { 26 #address-cells = <1>; 27 #size-cells = <1>; 28 ranges; 29 30 xtal: xtal { 31 #clock-cells = <0>; 32 compatible = "fixed-clock"; 33 clock-output-names = "xtal"; 34 }; 35 }; 36 37 ahb { 38 compatible = "simple-bus"; 39 ranges; 40 41 #address-cells = <1>; 42 #size-cells = <1>; 43 44 apb { 45 compatible = "simple-bus"; 46 ranges; 47 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 ehci0: ehci@1b000100 { 52 compatible = "generic-ehci"; 53 reg = <0x1b000100 0x100>; 54 55 status = "disabled"; 56 }; 57 58 uart0: uart@18020000 { 59 compatible = "ns16550"; 60 reg = <0x18020000 0x20>; 61 reg-shift = <2>; 62 63 status = "disabled"; 64 }; 65 66 gmac0: eth@0x19000000 { 67 compatible = "qca,ag934x-mac"; 68 reg = <0x19000000 0x200>; 69 phy = <&phy0>; 70 phy-mode = "rgmii"; 71 72 status = "disabled"; 73 74 mdio { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 phy0: ethernet-phy@0 { 78 reg = <0>; 79 }; 80 }; 81 }; 82 83 gmac1: eth@0x1a000000 { 84 compatible = "qca,ag934x-mac"; 85 reg = <0x1a000000 0x200>; 86 phy = <&phy1>; 87 phy-mode = "rgmii"; 88 89 status = "disabled"; 90 91 mdio { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 phy1: ethernet-phy@0 { 95 reg = <0>; 96 }; 97 }; 98 }; 99 }; 100 101 spi0: spi@1f000000 { 102 compatible = "qca,ar7100-spi"; 103 reg = <0x1f000000 0x10>; 104 105 status = "disabled"; 106 107 #address-cells = <1>; 108 #size-cells = <0>; 109 }; 110 }; 111}; 112