xref: /openbmc/u-boot/arch/mips/dts/ar933x.dtsi (revision c3155878)
16a7b52bcSWills Wang/*
26a7b52bcSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
36a7b52bcSWills Wang *
46a7b52bcSWills Wang * SPDX-License-Identifier: GPL-2.0+
56a7b52bcSWills Wang */
66a7b52bcSWills Wang
76a7b52bcSWills Wang#include <dt-bindings/interrupt-controller/irq.h>
86a7b52bcSWills Wang#include "skeleton.dtsi"
96a7b52bcSWills Wang
106a7b52bcSWills Wang/ {
116a7b52bcSWills Wang	compatible = "qca,ar933x";
126a7b52bcSWills Wang
136a7b52bcSWills Wang	#address-cells = <1>;
146a7b52bcSWills Wang	#size-cells = <1>;
156a7b52bcSWills Wang
166a7b52bcSWills Wang	cpus {
176a7b52bcSWills Wang		#address-cells = <1>;
186a7b52bcSWills Wang		#size-cells = <0>;
196a7b52bcSWills Wang
206a7b52bcSWills Wang		cpu@0 {
216a7b52bcSWills Wang			device_type = "cpu";
226a7b52bcSWills Wang			compatible = "mips,mips24Kc";
236a7b52bcSWills Wang			reg = <0>;
246a7b52bcSWills Wang		};
256a7b52bcSWills Wang	};
266a7b52bcSWills Wang
276a7b52bcSWills Wang	clocks {
286a7b52bcSWills Wang		#address-cells = <1>;
296a7b52bcSWills Wang		#size-cells = <1>;
306a7b52bcSWills Wang		ranges;
316a7b52bcSWills Wang
326a7b52bcSWills Wang		xtal: xtal {
336a7b52bcSWills Wang			#clock-cells = <0>;
346a7b52bcSWills Wang			compatible = "fixed-clock";
356a7b52bcSWills Wang			clock-output-names = "xtal";
366a7b52bcSWills Wang		};
376a7b52bcSWills Wang	};
386a7b52bcSWills Wang
396a7b52bcSWills Wang	pinctrl {
406a7b52bcSWills Wang		u-boot,dm-pre-reloc;
416a7b52bcSWills Wang		compatible = "qca,ar933x-pinctrl";
426a7b52bcSWills Wang		ranges;
436a7b52bcSWills Wang		#address-cells = <1>;
446a7b52bcSWills Wang		#size-cells = <1>;
456a7b52bcSWills Wang		reg = <0x18040000 0x100>;
466a7b52bcSWills Wang	};
476a7b52bcSWills Wang
486a7b52bcSWills Wang	ahb {
496a7b52bcSWills Wang		compatible = "simple-bus";
506a7b52bcSWills Wang		ranges;
516a7b52bcSWills Wang
526a7b52bcSWills Wang		#address-cells = <1>;
536a7b52bcSWills Wang		#size-cells = <1>;
546a7b52bcSWills Wang
556a7b52bcSWills Wang		apb {
566a7b52bcSWills Wang			compatible = "simple-bus";
576a7b52bcSWills Wang			ranges;
586a7b52bcSWills Wang
596a7b52bcSWills Wang			#address-cells = <1>;
606a7b52bcSWills Wang			#size-cells = <1>;
616a7b52bcSWills Wang
62*c3155878SMarek Vasut			ehci0: ehci@1b000100 {
63*c3155878SMarek Vasut				compatible = "generic-ehci";
64*c3155878SMarek Vasut				reg = <0x1b000100 0x100>;
65*c3155878SMarek Vasut
66*c3155878SMarek Vasut				status = "disabled";
67*c3155878SMarek Vasut			};
68*c3155878SMarek Vasut
696a7b52bcSWills Wang			uart0: uart@18020000 {
706a7b52bcSWills Wang				compatible = "qca,ar9330-uart";
716a7b52bcSWills Wang				reg = <0x18020000 0x20>;
726a7b52bcSWills Wang				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
736a7b52bcSWills Wang
746a7b52bcSWills Wang				status = "disabled";
756a7b52bcSWills Wang			};
766a7b52bcSWills Wang		};
776a7b52bcSWills Wang
786a7b52bcSWills Wang		spi0: spi@1f000000 {
796a7b52bcSWills Wang			compatible = "qca,ar7100-spi";
806a7b52bcSWills Wang			reg = <0x1f000000 0x10>;
816a7b52bcSWills Wang			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
826a7b52bcSWills Wang
836a7b52bcSWills Wang			status = "disabled";
846a7b52bcSWills Wang
856a7b52bcSWills Wang			#address-cells = <1>;
866a7b52bcSWills Wang			#size-cells = <0>;
876a7b52bcSWills Wang		};
886a7b52bcSWills Wang	};
896a7b52bcSWills Wang};
90