xref: /openbmc/u-boot/arch/mips/dts/ar933x.dtsi (revision 6a7b52bc)
1*6a7b52bcSWills Wang/*
2*6a7b52bcSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3*6a7b52bcSWills Wang *
4*6a7b52bcSWills Wang * SPDX-License-Identifier: GPL-2.0+
5*6a7b52bcSWills Wang */
6*6a7b52bcSWills Wang
7*6a7b52bcSWills Wang#include <dt-bindings/interrupt-controller/irq.h>
8*6a7b52bcSWills Wang#include "skeleton.dtsi"
9*6a7b52bcSWills Wang
10*6a7b52bcSWills Wang/ {
11*6a7b52bcSWills Wang	compatible = "qca,ar933x";
12*6a7b52bcSWills Wang
13*6a7b52bcSWills Wang	#address-cells = <1>;
14*6a7b52bcSWills Wang	#size-cells = <1>;
15*6a7b52bcSWills Wang
16*6a7b52bcSWills Wang	cpus {
17*6a7b52bcSWills Wang		#address-cells = <1>;
18*6a7b52bcSWills Wang		#size-cells = <0>;
19*6a7b52bcSWills Wang
20*6a7b52bcSWills Wang		cpu@0 {
21*6a7b52bcSWills Wang			device_type = "cpu";
22*6a7b52bcSWills Wang			compatible = "mips,mips24Kc";
23*6a7b52bcSWills Wang			reg = <0>;
24*6a7b52bcSWills Wang		};
25*6a7b52bcSWills Wang	};
26*6a7b52bcSWills Wang
27*6a7b52bcSWills Wang	clocks {
28*6a7b52bcSWills Wang		#address-cells = <1>;
29*6a7b52bcSWills Wang		#size-cells = <1>;
30*6a7b52bcSWills Wang		ranges;
31*6a7b52bcSWills Wang
32*6a7b52bcSWills Wang		xtal: xtal {
33*6a7b52bcSWills Wang			#clock-cells = <0>;
34*6a7b52bcSWills Wang			compatible = "fixed-clock";
35*6a7b52bcSWills Wang			clock-output-names = "xtal";
36*6a7b52bcSWills Wang		};
37*6a7b52bcSWills Wang	};
38*6a7b52bcSWills Wang
39*6a7b52bcSWills Wang	pinctrl {
40*6a7b52bcSWills Wang		u-boot,dm-pre-reloc;
41*6a7b52bcSWills Wang		compatible = "qca,ar933x-pinctrl";
42*6a7b52bcSWills Wang		ranges;
43*6a7b52bcSWills Wang		#address-cells = <1>;
44*6a7b52bcSWills Wang		#size-cells = <1>;
45*6a7b52bcSWills Wang		reg = <0x18040000 0x100>;
46*6a7b52bcSWills Wang	};
47*6a7b52bcSWills Wang
48*6a7b52bcSWills Wang	ahb {
49*6a7b52bcSWills Wang		compatible = "simple-bus";
50*6a7b52bcSWills Wang		ranges;
51*6a7b52bcSWills Wang
52*6a7b52bcSWills Wang		#address-cells = <1>;
53*6a7b52bcSWills Wang		#size-cells = <1>;
54*6a7b52bcSWills Wang
55*6a7b52bcSWills Wang		apb {
56*6a7b52bcSWills Wang			compatible = "simple-bus";
57*6a7b52bcSWills Wang			ranges;
58*6a7b52bcSWills Wang
59*6a7b52bcSWills Wang			#address-cells = <1>;
60*6a7b52bcSWills Wang			#size-cells = <1>;
61*6a7b52bcSWills Wang
62*6a7b52bcSWills Wang			uart0: uart@18020000 {
63*6a7b52bcSWills Wang				compatible = "qca,ar9330-uart";
64*6a7b52bcSWills Wang				reg = <0x18020000 0x20>;
65*6a7b52bcSWills Wang				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
66*6a7b52bcSWills Wang
67*6a7b52bcSWills Wang				status = "disabled";
68*6a7b52bcSWills Wang			};
69*6a7b52bcSWills Wang		};
70*6a7b52bcSWills Wang
71*6a7b52bcSWills Wang		spi0: spi@1f000000 {
72*6a7b52bcSWills Wang			compatible = "qca,ar7100-spi";
73*6a7b52bcSWills Wang			reg = <0x1f000000 0x10>;
74*6a7b52bcSWills Wang			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
75*6a7b52bcSWills Wang
76*6a7b52bcSWills Wang			status = "disabled";
77*6a7b52bcSWills Wang
78*6a7b52bcSWills Wang			#address-cells = <1>;
79*6a7b52bcSWills Wang			#size-cells = <0>;
80*6a7b52bcSWills Wang		};
81*6a7b52bcSWills Wang	};
82*6a7b52bcSWills Wang};
83