16a7b52bcSWills Wang/* 26a7b52bcSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 36a7b52bcSWills Wang * 46a7b52bcSWills Wang * SPDX-License-Identifier: GPL-2.0+ 56a7b52bcSWills Wang */ 66a7b52bcSWills Wang 76a7b52bcSWills Wang#include <dt-bindings/interrupt-controller/irq.h> 86a7b52bcSWills Wang#include "skeleton.dtsi" 96a7b52bcSWills Wang 106a7b52bcSWills Wang/ { 116a7b52bcSWills Wang compatible = "qca,ar933x"; 126a7b52bcSWills Wang 136a7b52bcSWills Wang #address-cells = <1>; 146a7b52bcSWills Wang #size-cells = <1>; 156a7b52bcSWills Wang 166a7b52bcSWills Wang cpus { 176a7b52bcSWills Wang #address-cells = <1>; 186a7b52bcSWills Wang #size-cells = <0>; 196a7b52bcSWills Wang 206a7b52bcSWills Wang cpu@0 { 216a7b52bcSWills Wang device_type = "cpu"; 226a7b52bcSWills Wang compatible = "mips,mips24Kc"; 236a7b52bcSWills Wang reg = <0>; 246a7b52bcSWills Wang }; 256a7b52bcSWills Wang }; 266a7b52bcSWills Wang 276a7b52bcSWills Wang clocks { 286a7b52bcSWills Wang #address-cells = <1>; 296a7b52bcSWills Wang #size-cells = <1>; 306a7b52bcSWills Wang ranges; 316a7b52bcSWills Wang 326a7b52bcSWills Wang xtal: xtal { 336a7b52bcSWills Wang #clock-cells = <0>; 346a7b52bcSWills Wang compatible = "fixed-clock"; 356a7b52bcSWills Wang clock-output-names = "xtal"; 366a7b52bcSWills Wang }; 376a7b52bcSWills Wang }; 386a7b52bcSWills Wang 396a7b52bcSWills Wang pinctrl { 406a7b52bcSWills Wang u-boot,dm-pre-reloc; 416a7b52bcSWills Wang compatible = "qca,ar933x-pinctrl"; 426a7b52bcSWills Wang ranges; 436a7b52bcSWills Wang #address-cells = <1>; 446a7b52bcSWills Wang #size-cells = <1>; 456a7b52bcSWills Wang reg = <0x18040000 0x100>; 466a7b52bcSWills Wang }; 476a7b52bcSWills Wang 486a7b52bcSWills Wang ahb { 496a7b52bcSWills Wang compatible = "simple-bus"; 506a7b52bcSWills Wang ranges; 516a7b52bcSWills Wang 526a7b52bcSWills Wang #address-cells = <1>; 536a7b52bcSWills Wang #size-cells = <1>; 546a7b52bcSWills Wang 556a7b52bcSWills Wang apb { 566a7b52bcSWills Wang compatible = "simple-bus"; 576a7b52bcSWills Wang ranges; 586a7b52bcSWills Wang 596a7b52bcSWills Wang #address-cells = <1>; 606a7b52bcSWills Wang #size-cells = <1>; 616a7b52bcSWills Wang 62c3155878SMarek Vasut ehci0: ehci@1b000100 { 63c3155878SMarek Vasut compatible = "generic-ehci"; 64c3155878SMarek Vasut reg = <0x1b000100 0x100>; 65c3155878SMarek Vasut 66c3155878SMarek Vasut status = "disabled"; 67c3155878SMarek Vasut }; 68c3155878SMarek Vasut 696a7b52bcSWills Wang uart0: uart@18020000 { 706a7b52bcSWills Wang compatible = "qca,ar9330-uart"; 716a7b52bcSWills Wang reg = <0x18020000 0x20>; 726a7b52bcSWills Wang interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; 736a7b52bcSWills Wang 746a7b52bcSWills Wang status = "disabled"; 756a7b52bcSWills Wang }; 762986a9d4SMarek Vasut 772986a9d4SMarek Vasut gmac0: eth@0x19000000 { 78*04583c68SWills Wang compatible = "qca,ag933x-mac"; 792986a9d4SMarek Vasut reg = <0x19000000 0x200>; 802986a9d4SMarek Vasut phy = <&phy0>; 812986a9d4SMarek Vasut phy-mode = "rmii"; 822986a9d4SMarek Vasut 832986a9d4SMarek Vasut status = "disabled"; 842986a9d4SMarek Vasut 852986a9d4SMarek Vasut mdio { 862986a9d4SMarek Vasut #address-cells = <1>; 872986a9d4SMarek Vasut #size-cells = <0>; 882986a9d4SMarek Vasut phy0: ethernet-phy@0 { 892986a9d4SMarek Vasut reg = <0>; 902986a9d4SMarek Vasut }; 912986a9d4SMarek Vasut }; 922986a9d4SMarek Vasut }; 932986a9d4SMarek Vasut 942986a9d4SMarek Vasut gmac1: eth@0x1a000000 { 95*04583c68SWills Wang compatible = "qca,ag933x-mac"; 962986a9d4SMarek Vasut reg = <0x1a000000 0x200>; 972986a9d4SMarek Vasut phy = <&phy0>; 982986a9d4SMarek Vasut phy-mode = "rgmii"; 992986a9d4SMarek Vasut 1002986a9d4SMarek Vasut status = "disabled"; 1012986a9d4SMarek Vasut }; 1026a7b52bcSWills Wang }; 1036a7b52bcSWills Wang 1046a7b52bcSWills Wang spi0: spi@1f000000 { 1056a7b52bcSWills Wang compatible = "qca,ar7100-spi"; 1066a7b52bcSWills Wang reg = <0x1f000000 0x10>; 1076a7b52bcSWills Wang interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; 1086a7b52bcSWills Wang 1096a7b52bcSWills Wang status = "disabled"; 1106a7b52bcSWills Wang 1116a7b52bcSWills Wang #address-cells = <1>; 1126a7b52bcSWills Wang #size-cells = <0>; 1136a7b52bcSWills Wang }; 1146a7b52bcSWills Wang }; 1156a7b52bcSWills Wang}; 116