xref: /openbmc/u-boot/arch/mips/cpu/start.S (revision e9c847c3) 
1/*
2 *  Startup Code for MIPS32 CPU-core
3 *
4 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
15#ifndef CONFIG_SYS_INIT_SP_ADDR
16#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
17				CONFIG_SYS_INIT_SP_OFFSET)
18#endif
19
20#ifdef CONFIG_32BIT
21# define MIPS_RELOC	3
22# define STATUS_SET	0
23#endif
24
25#ifdef CONFIG_64BIT
26# ifdef CONFIG_SYS_LITTLE_ENDIAN
27#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29# else
30#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32# endif
33# define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34# define STATUS_SET	ST0_KX
35#endif
36
37	.set noreorder
38
39	.macro init_wr sel
40	MTC0	zero, CP0_WATCHLO,\sel
41	mtc0	t1, CP0_WATCHHI,\sel
42	mfc0	t0, CP0_WATCHHI,\sel
43	bgez	t0, wr_done
44	 nop
45	.endm
46
47	.macro uhi_mips_exception
48	move	k0, t9		# preserve t9 in k0
49	move	k1, a0		# preserve a0 in k1
50	li	t9, 15		# UHI exception operation
51	li	a0, 0		# Use hard register context
52	sdbbp	1		# Invoke UHI operation
53	.endm
54
55	.macro setup_stack_gd
56	li	t0, -16
57	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
58	and	sp, t1, t0		# force 16 byte alignment
59	PTR_SUBU \
60		sp, sp, GD_SIZE		# reserve space for gd
61	and	sp, sp, t0		# force 16 byte alignment
62	move	k0, sp			# save gd pointer
63#ifdef CONFIG_SYS_MALLOC_F_LEN
64	li	t2, CONFIG_SYS_MALLOC_F_LEN
65	PTR_SUBU \
66		sp, sp, t2		# reserve space for early malloc
67	and	sp, sp, t0		# force 16 byte alignment
68#endif
69	move	fp, sp
70
71	/* Clear gd */
72	move	t0, k0
731:
74	PTR_S	zero, 0(t0)
75	blt	t0, t1, 1b
76	 PTR_ADDIU t0, PTRSIZE
77
78#ifdef CONFIG_SYS_MALLOC_F_LEN
79	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
80#endif
81	.endm
82
83ENTRY(_start)
84	/* U-Boot entry point */
85	b	reset
86	 mtc0	zero, CP0_COUNT	# clear cp0 count for most accurate boot timing
87
88#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
89	/*
90	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
91	 * access external NOR flashes. If the board boots from NOR flash the
92	 * internal BootROM does a blind read at address 0xB0000010 to read the
93	 * initial configuration for that EBU in order to access the flash
94	 * device with correct parameters. This config option is board-specific.
95	 */
96	.org 0x10
97	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
98	.word 0x0
99#endif
100#if defined(CONFIG_MALTA)
101	/*
102	 * Linux expects the Board ID here.
103	 */
104	.org 0x10
105	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
106	.word 0x00000000
107#endif
108
109#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
110	/*
111	 * Exception vector entry points. When running from ROM, an exception
112	 * cannot be handled. Halt execution and transfer control to debugger,
113	 * if one is attached.
114	 */
115	.org 0x200
116	/* TLB refill, 32 bit task */
117	uhi_mips_exception
118
119	.org 0x280
120	/* XTLB refill, 64 bit task */
121	uhi_mips_exception
122
123	.org 0x300
124	/* Cache error exception */
125	uhi_mips_exception
126
127	.org 0x380
128	/* General exception */
129	uhi_mips_exception
130
131	.org 0x400
132	/* Catch interrupt exceptions */
133	uhi_mips_exception
134
135	.org 0x480
136	/* EJTAG debug exception */
1371:	b	1b
138	 nop
139
140	.org 0x500
141#endif
142
143reset:
144#if __mips_isa_rev >= 6
145	mfc0	t0, CP0_CONFIG, 5
146	and	t0, t0, MIPS_CONF5_VP
147	beqz	t0, 1f
148	 nop
149
150	b	2f
151	 mfc0	t0, CP0_GLOBALNUMBER
152#endif
153
1541:	mfc0	t0, CP0_EBASE
155	and	t0, t0, EBASE_CPUNUM
156
157	/* Hang if this isn't the first CPU in the system */
1582:	beqz	t0, 4f
159	 nop
1603:	wait
161	b	3b
162	 nop
163
164	/* Init CP0 Status */
1654:	mfc0	t0, CP0_STATUS
166	and	t0, ST0_IMPL
167	or	t0, ST0_BEV | ST0_ERL | STATUS_SET
168	mtc0	t0, CP0_STATUS
169
170	/*
171	 * Check whether CP0 Config1 is implemented. If not continue
172	 * with legacy Watch register initialization.
173	 */
174	mfc0	t0, CP0_CONFIG
175	bgez	t0, wr_legacy
176	 nop
177
178	/*
179	 * Check WR bit in CP0 Config1 to determine if Watch registers
180	 * are implemented.
181	 */
182	mfc0	t0, CP0_CONFIG, 1
183	andi	t0, (1 << 3)
184	beqz	t0, wr_done
185	 nop
186
187	/* Clear Watch Status bits and disable watch exceptions */
188	li	t1, 0x7		# Clear I, R and W conditions
189	init_wr	0
190	init_wr	1
191	init_wr	2
192	init_wr	3
193	init_wr	4
194	init_wr	5
195	init_wr	6
196	init_wr	7
197	b	wr_done
198	 nop
199
200wr_legacy:
201	MTC0	zero, CP0_WATCHLO
202	mtc0	zero, CP0_WATCHHI
203
204wr_done:
205	/* Clear WP, IV and SW interrupts */
206	mtc0	zero, CP0_CAUSE
207
208	/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
209	mtc0	zero, CP0_COMPARE
210
211#ifndef CONFIG_SKIP_LOWLEVEL_INIT
212	mfc0	t0, CP0_CONFIG
213	and	t0, t0, MIPS_CONF_IMPL
214	or	t0, t0, CONF_CM_UNCACHED
215	mtc0	t0, CP0_CONFIG
216	ehb
217#endif
218
219	/*
220	 * Initialize $gp, force pointer sized alignment of bal instruction to
221	 * forbid the compiler to put nop's between bal and _gp. This is
222	 * required to keep _gp and ra aligned to 8 byte.
223	 */
224	.align	PTRLOG
225	bal	1f
226	 nop
227	PTR	_gp
2281:
229	PTR_L	gp, 0(ra)
230
231#ifdef CONFIG_MIPS_CM
232	PTR_LA	t9, mips_cm_map
233	jalr	t9
234	 nop
235#endif
236
237#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
238	/* Set up initial stack and global data */
239	setup_stack_gd
240#endif
241
242#ifndef CONFIG_SKIP_LOWLEVEL_INIT
243# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
244	/* Initialize any external memory */
245	PTR_LA	t9, lowlevel_init
246	jalr	t9
247	 nop
248# endif
249
250	/* Initialize caches... */
251	PTR_LA	t9, mips_cache_reset
252	jalr	t9
253	 nop
254
255# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
256	/* Initialize any external memory */
257	PTR_LA	t9, lowlevel_init
258	jalr	t9
259	 nop
260# endif
261#endif
262
263#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
264	/* Set up initial stack and global data */
265	setup_stack_gd
266#endif
267
268	move	a0, zero		# a0 <-- boot_flags = 0
269	PTR_LA	t9, board_init_f
270
271	jr	t9
272	 move	ra, zero
273
274	END(_start)
275
276/*
277 * void relocate_code (addr_sp, gd, addr_moni)
278 *
279 * This "function" does not return, instead it continues in RAM
280 * after relocating the monitor code.
281 *
282 * a0 = addr_sp
283 * a1 = gd
284 * a2 = destination address
285 */
286ENTRY(relocate_code)
287	move	sp, a0			# set new stack pointer
288	move	fp, sp
289
290	move	s0, a1			# save gd in s0
291	move	s2, a2			# save destination address in s2
292
293	PTR_LI	t0, CONFIG_SYS_MONITOR_BASE
294	PTR_SUB	s1, s2, t0		# s1 <-- relocation offset
295
296	PTR_LA	t2, __image_copy_end
297	move	t1, a2
298
299	/*
300	 * t0 = source address
301	 * t1 = target address
302	 * t2 = source end address
303	 */
3041:
305	PTR_L	t3, 0(t0)
306	PTR_S	t3, 0(t1)
307	PTR_ADDU t0, PTRSIZE
308	blt	t0, t2, 1b
309	 PTR_ADDU t1, PTRSIZE
310
311	/*
312	 * Now we want to update GOT.
313	 *
314	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
315	 * generated by GNU ld. Skip these reserved entries from relocation.
316	 */
317	PTR_LA	t3, num_got_entries
318	PTR_LA	t8, _GLOBAL_OFFSET_TABLE_
319	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
320	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
321	PTR_LI	t2, 2
3221:
323	PTR_L	t1, 0(t8)
324	beqz	t1, 2f
325	 PTR_ADD t1, s1
326	PTR_S	t1, 0(t8)
3272:
328	PTR_ADDIU t2, 1
329	blt	t2, t3, 1b
330	 PTR_ADDIU t8, PTRSIZE
331
332	/* Update dynamic relocations */
333	PTR_LA	t1, __rel_dyn_start
334	PTR_LA	t2, __rel_dyn_end
335
336	b	2f			# skip first reserved entry
337	 PTR_ADDIU t1, 2 * PTRSIZE
338
3391:
340	lw	t8, -4(t1)		# t8 <-- relocation info
341
342	PTR_LI	t3, MIPS_RELOC
343	bne	t8, t3, 2f		# skip non-MIPS_RELOC entries
344	 nop
345
346	PTR_L	t3, -(2 * PTRSIZE)(t1)	# t3 <-- location to fix up in FLASH
347
348	PTR_L	t8, 0(t3)		# t8 <-- original pointer
349	PTR_ADD	t8, s1			# t8 <-- adjusted pointer
350
351	PTR_ADD	t3, s1			# t3 <-- location to fix up in RAM
352	PTR_S	t8, 0(t3)
353
3542:
355	blt	t1, t2, 1b
356	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
357
358	/*
359	 * Flush caches to ensure our newly modified instructions are visible
360	 * to the instruction cache. We're still running with the old GOT, so
361	 * apply the reloc offset to the start address.
362	 */
363	PTR_LA	a0, __text_start
364	PTR_LA	a1, __text_end
365	PTR_SUB	a1, a1, a0
366	PTR_LA	t9, flush_cache
367	jalr	t9
368	 PTR_ADD	a0, s1
369
370	PTR_ADD	gp, s1			# adjust gp
371
372	/*
373	 * Clear BSS
374	 *
375	 * GOT is now relocated. Thus __bss_start and __bss_end can be
376	 * accessed directly via $gp.
377	 */
378	PTR_LA	t1, __bss_start		# t1 <-- __bss_start
379	PTR_LA	t2, __bss_end		# t2 <-- __bss_end
380
3811:
382	PTR_S	zero, 0(t1)
383	blt	t1, t2, 1b
384	 PTR_ADDIU t1, PTRSIZE
385
386	move	a0, s0			# a0 <-- gd
387	move	a1, s2
388	PTR_LA	t9, board_init_r
389	jr	t9
390	 move	ra, zero
391
392	END(relocate_code)
393