xref: /openbmc/u-boot/arch/mips/cpu/start.S (revision b419e872) 
1/*
2 *  Startup Code for MIPS32 CPU-core
3 *
4 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
15#ifndef CONFIG_SYS_INIT_SP_ADDR
16#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
17				CONFIG_SYS_INIT_SP_OFFSET)
18#endif
19
20#ifdef CONFIG_32BIT
21# define MIPS_RELOC	3
22# define STATUS_SET	0
23#endif
24
25#ifdef CONFIG_64BIT
26# ifdef CONFIG_SYS_LITTLE_ENDIAN
27#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29# else
30#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32# endif
33# define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34# define STATUS_SET	ST0_KX
35#endif
36
37	/*
38	 * For the moment disable interrupts, mark the kernel mode and
39	 * set ST0_KX so that the CPU does not spit fire when using
40	 * 64-bit addresses.
41	 */
42	.macro	setup_c0_status set clr
43	.set	push
44	mfc0	t0, CP0_STATUS
45	or	t0, ST0_CU0 | \set | 0x1f | \clr
46	xor	t0, 0x1f | \clr
47	mtc0	t0, CP0_STATUS
48	.set	noreorder
49	sll	zero, 3				# ehb
50	.set	pop
51	.endm
52
53	.set noreorder
54
55ENTRY(_start)
56	/* U-Boot entry point */
57	b	reset
58	 nop
59
60	.org 0x10
61#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
62	/*
63	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
64	 * access external NOR flashes. If the board boots from NOR flash the
65	 * internal BootROM does a blind read at address 0xB0000010 to read the
66	 * initial configuration for that EBU in order to access the flash
67	 * device with correct parameters. This config option is board-specific.
68	 */
69	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
70	.word 0x0
71#elif defined(CONFIG_MALTA)
72	/*
73	 * Linux expects the Board ID here.
74	 */
75	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
76	.word 0x00000000
77#endif
78
79	.org 0x200
80	/* TLB refill, 32 bit task */
811:	b	1b
82	 nop
83
84	.org 0x280
85	/* XTLB refill, 64 bit task */
861:	b	1b
87	 nop
88
89	.org 0x300
90	/* Cache error exception */
911:	b	1b
92	 nop
93
94	.org 0x380
95	/* General exception */
961:	b	1b
97	 nop
98
99	.org 0x400
100	/* Catch interrupt exceptions */
1011:	b	1b
102	 nop
103
104	.org 0x480
105	/* EJTAG debug exception */
1061:	b	1b
107	 nop
108
109	.align 4
110reset:
111
112	/* Clear watch registers */
113	MTC0	zero, CP0_WATCHLO
114	mtc0	zero, CP0_WATCHHI
115
116	/* WP(Watch Pending), SW0/1 should be cleared */
117	mtc0	zero, CP0_CAUSE
118
119	setup_c0_status STATUS_SET 0
120
121	/* Init Timer */
122	mtc0	zero, CP0_COUNT
123	mtc0	zero, CP0_COMPARE
124
125#ifndef CONFIG_SKIP_LOWLEVEL_INIT
126	mfc0	t0, CP0_CONFIG
127	and	t0, t0, MIPS_CONF_IMPL
128	or	t0, t0, CONF_CM_UNCACHED
129	mtc0	t0, CP0_CONFIG
130	ehb
131#endif
132
133	/*
134	 * Initialize $gp, force pointer sized alignment of bal instruction to
135	 * forbid the compiler to put nop's between bal and _gp. This is
136	 * required to keep _gp and ra aligned to 8 byte.
137	 */
138	.align	PTRLOG
139	bal	1f
140	 nop
141	PTR	_gp
1421:
143	PTR_L	gp, 0(ra)
144
145#ifdef CONFIG_MIPS_CM
146	PTR_LA	t9, mips_cm_map
147	jalr	t9
148	 nop
149#endif
150
151#ifndef CONFIG_SKIP_LOWLEVEL_INIT
152# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
153	/* Initialize any external memory */
154	PTR_LA	t9, lowlevel_init
155	jalr	t9
156	 nop
157# endif
158
159	/* Initialize caches... */
160	PTR_LA	t9, mips_cache_reset
161	jalr	t9
162	 nop
163
164# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
165	/* Initialize any external memory */
166	PTR_LA	t9, lowlevel_init
167	jalr	t9
168	 nop
169# endif
170#endif
171
172	/* Set up temporary stack */
173	li	t0, -16
174	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
175	and	sp, t1, t0		# force 16 byte alignment
176	PTR_SUBU \
177		sp, sp, GD_SIZE		# reserve space for gd
178	and	sp, sp, t0		# force 16 byte alignment
179	move	k0, sp			# save gd pointer
180#ifdef CONFIG_SYS_MALLOC_F_LEN
181	li	t2, CONFIG_SYS_MALLOC_F_LEN
182	PTR_SUBU \
183		sp, sp, t2		# reserve space for early malloc
184	and	sp, sp, t0		# force 16 byte alignment
185#endif
186	move	fp, sp
187
188	/* Clear gd */
189	move	t0, k0
1901:
191	PTR_S	zero, 0(t0)
192	blt	t0, t1, 1b
193	 PTR_ADDIU t0, PTRSIZE
194
195#ifdef CONFIG_SYS_MALLOC_F_LEN
196	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
197#endif
198
199	move	a0, zero		# a0 <-- boot_flags = 0
200	PTR_LA	t9, board_init_f
201	jr	t9
202	 move	ra, zero
203
204	END(_start)
205
206/*
207 * void relocate_code (addr_sp, gd, addr_moni)
208 *
209 * This "function" does not return, instead it continues in RAM
210 * after relocating the monitor code.
211 *
212 * a0 = addr_sp
213 * a1 = gd
214 * a2 = destination address
215 */
216ENTRY(relocate_code)
217	move	sp, a0			# set new stack pointer
218	move	fp, sp
219
220	move	s0, a1			# save gd in s0
221	move	s2, a2			# save destination address in s2
222
223	PTR_LI	t0, CONFIG_SYS_MONITOR_BASE
224	PTR_SUB	s1, s2, t0		# s1 <-- relocation offset
225
226	PTR_LA	t3, in_ram
227	PTR_L	t2, -(3 * PTRSIZE)(t3)	# t2 <-- __image_copy_end
228	move	t1, a2
229
230	PTR_ADD	gp, s1			# adjust gp
231
232	/*
233	 * t0 = source address
234	 * t1 = target address
235	 * t2 = source end address
236	 */
2371:
238	PTR_L	t3, 0(t0)
239	PTR_S	t3, 0(t1)
240	PTR_ADDU t0, PTRSIZE
241	blt	t0, t2, 1b
242	 PTR_ADDU t1, PTRSIZE
243
244	/* If caches were enabled, we would have to flush them here. */
245	PTR_SUB	a1, t1, s2		# a1 <-- size
246	PTR_LA	t9, flush_cache
247	jalr	t9
248	 move	a0, s2			# a0 <-- destination address
249
250	/* Jump to where we've relocated ourselves */
251	PTR_ADDIU t0, s2, in_ram - _start
252	jr	t0
253	 nop
254
255	PTR	__rel_dyn_end
256	PTR	__rel_dyn_start
257	PTR	__image_copy_end
258	PTR	_GLOBAL_OFFSET_TABLE_
259	PTR	num_got_entries
260
261in_ram:
262	/*
263	 * Now we want to update GOT.
264	 *
265	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
266	 * generated by GNU ld. Skip these reserved entries from relocation.
267	 */
268	PTR_L	t3, -(1 * PTRSIZE)(t0)	# t3 <-- num_got_entries
269	PTR_L	t8, -(2 * PTRSIZE)(t0)	# t8 <-- _GLOBAL_OFFSET_TABLE_
270	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
271	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
272	PTR_LI	t2, 2
2731:
274	PTR_L	t1, 0(t8)
275	beqz	t1, 2f
276	 PTR_ADD t1, s1
277	PTR_S	t1, 0(t8)
2782:
279	PTR_ADDIU t2, 1
280	blt	t2, t3, 1b
281	 PTR_ADDIU t8, PTRSIZE
282
283	/* Update dynamic relocations */
284	PTR_L	t1, -(4 * PTRSIZE)(t0)	# t1 <-- __rel_dyn_start
285	PTR_L	t2, -(5 * PTRSIZE)(t0)	# t2 <-- __rel_dyn_end
286
287	b	2f			# skip first reserved entry
288	 PTR_ADDIU t1, 2 * PTRSIZE
289
2901:
291	lw	t8, -4(t1)		# t8 <-- relocation info
292
293	PTR_LI	t3, MIPS_RELOC
294	bne	t8, t3, 2f		# skip non-MIPS_RELOC entries
295	 nop
296
297	PTR_L	t3, -(2 * PTRSIZE)(t1)	# t3 <-- location to fix up in FLASH
298
299	PTR_L	t8, 0(t3)		# t8 <-- original pointer
300	PTR_ADD	t8, s1			# t8 <-- adjusted pointer
301
302	PTR_ADD	t3, s1			# t3 <-- location to fix up in RAM
303	PTR_S	t8, 0(t3)
304
3052:
306	blt	t1, t2, 1b
307	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
308
309	/*
310	 * Clear BSS
311	 *
312	 * GOT is now relocated. Thus __bss_start and __bss_end can be
313	 * accessed directly via $gp.
314	 */
315	PTR_LA	t1, __bss_start		# t1 <-- __bss_start
316	PTR_LA	t2, __bss_end		# t2 <-- __bss_end
317
3181:
319	PTR_S	zero, 0(t1)
320	blt	t1, t2, 1b
321	 PTR_ADDIU t1, PTRSIZE
322
323	move	a0, s0			# a0 <-- gd
324	move	a1, s2
325	PTR_LA	t9, board_init_r
326	jr	t9
327	 move	ra, zero
328
329	END(relocate_code)
330