xref: /openbmc/u-boot/arch/mips/cpu/start.S (revision 699c4e59) 
1/*
2 *  Startup Code for MIPS32 CPU-core
3 *
4 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
15#ifndef CONFIG_SYS_MIPS_CACHE_MODE
16#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
17#endif
18
19#ifndef CONFIG_SYS_INIT_SP_ADDR
20#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
21				CONFIG_SYS_INIT_SP_OFFSET)
22#endif
23
24#ifdef CONFIG_32BIT
25# define MIPS_RELOC	3
26# define STATUS_SET	0
27#endif
28
29#ifdef CONFIG_64BIT
30# ifdef CONFIG_SYS_LITTLE_ENDIAN
31#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
32	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
33# else
34#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
35	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
36# endif
37# define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
38# define STATUS_SET	ST0_KX
39#endif
40
41	/*
42	 * For the moment disable interrupts, mark the kernel mode and
43	 * set ST0_KX so that the CPU does not spit fire when using
44	 * 64-bit addresses.
45	 */
46	.macro	setup_c0_status set clr
47	.set	push
48	mfc0	t0, CP0_STATUS
49	or	t0, ST0_CU0 | \set | 0x1f | \clr
50	xor	t0, 0x1f | \clr
51	mtc0	t0, CP0_STATUS
52	.set	noreorder
53	sll	zero, 3				# ehb
54	.set	pop
55	.endm
56
57	.set noreorder
58
59ENTRY(_start)
60	/* U-Boot entry point */
61	b	reset
62	 nop
63
64	.org 0x10
65#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
66	/*
67	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
68	 * access external NOR flashes. If the board boots from NOR flash the
69	 * internal BootROM does a blind read at address 0xB0000010 to read the
70	 * initial configuration for that EBU in order to access the flash
71	 * device with correct parameters. This config option is board-specific.
72	 */
73	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
74	.word 0x0
75#elif defined(CONFIG_MALTA)
76	/*
77	 * Linux expects the Board ID here.
78	 */
79	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
80	.word 0x00000000
81#endif
82
83	.org 0x200
84	/* TLB refill, 32 bit task */
851:	b	1b
86	 nop
87
88	.org 0x280
89	/* XTLB refill, 64 bit task */
901:	b	1b
91	 nop
92
93	.org 0x300
94	/* Cache error exception */
951:	b	1b
96	 nop
97
98	.org 0x380
99	/* General exception */
1001:	b	1b
101	 nop
102
103	.org 0x400
104	/* Catch interrupt exceptions */
1051:	b	1b
106	 nop
107
108	.org 0x480
109	/* EJTAG debug exception */
1101:	b	1b
111	 nop
112
113	.align 4
114reset:
115
116	/* Clear watch registers */
117	MTC0	zero, CP0_WATCHLO
118	mtc0	zero, CP0_WATCHHI
119
120	/* WP(Watch Pending), SW0/1 should be cleared */
121	mtc0	zero, CP0_CAUSE
122
123	setup_c0_status STATUS_SET 0
124
125	/* Init Timer */
126	mtc0	zero, CP0_COUNT
127	mtc0	zero, CP0_COMPARE
128
129#ifndef CONFIG_SKIP_LOWLEVEL_INIT
130	/* CONFIG0 register */
131	li	t0, CONF_CM_UNCACHED
132	mtc0	t0, CP0_CONFIG
133#endif
134
135	/*
136	 * Initialize $gp, force pointer sized alignment of bal instruction to
137	 * forbid the compiler to put nop's between bal and _gp. This is
138	 * required to keep _gp and ra aligned to 8 byte.
139	 */
140	.align	PTRLOG
141	bal	1f
142	 nop
143	PTR	_gp
1441:
145	PTR_L	gp, 0(ra)
146
147#ifndef CONFIG_SKIP_LOWLEVEL_INIT
148	/* Initialize any external memory */
149	PTR_LA	t9, lowlevel_init
150	jalr	t9
151	 nop
152
153	/* Initialize caches... */
154	PTR_LA	t9, mips_cache_reset
155	jalr	t9
156	 nop
157
158	/* ... and enable them */
159	li	t0, CONFIG_SYS_MIPS_CACHE_MODE
160	mtc0	t0, CP0_CONFIG
161#endif
162
163	/* Set up temporary stack */
164	li	t0, -16
165	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
166	and	sp, t1, t0		# force 16 byte alignment
167	PTR_SUBU \
168		sp, sp, GD_SIZE		# reserve space for gd
169	and	sp, sp, t0		# force 16 byte alignment
170	move	k0, sp			# save gd pointer
171#ifdef CONFIG_SYS_MALLOC_F_LEN
172	li	t2, CONFIG_SYS_MALLOC_F_LEN
173	PTR_SUBU \
174		sp, sp, t2		# reserve space for early malloc
175	and	sp, sp, t0		# force 16 byte alignment
176#endif
177	move	fp, sp
178
179	/* Clear gd */
180	move	t0, k0
1811:
182	PTR_S	zero, 0(t0)
183	blt	t0, t1, 1b
184	 PTR_ADDIU t0, PTRSIZE
185
186#ifdef CONFIG_SYS_MALLOC_F_LEN
187	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
188#endif
189
190	move	a0, zero		# a0 <-- boot_flags = 0
191	PTR_LA	t9, board_init_f
192	jr	t9
193	 move	ra, zero
194
195	END(_start)
196
197/*
198 * void relocate_code (addr_sp, gd, addr_moni)
199 *
200 * This "function" does not return, instead it continues in RAM
201 * after relocating the monitor code.
202 *
203 * a0 = addr_sp
204 * a1 = gd
205 * a2 = destination address
206 */
207ENTRY(relocate_code)
208	move	sp, a0			# set new stack pointer
209	move	fp, sp
210
211	move	s0, a1			# save gd in s0
212	move	s2, a2			# save destination address in s2
213
214	PTR_LI	t0, CONFIG_SYS_MONITOR_BASE
215	PTR_SUB	s1, s2, t0		# s1 <-- relocation offset
216
217	PTR_LA	t3, in_ram
218	PTR_L	t2, -(3 * PTRSIZE)(t3)	# t2 <-- __image_copy_end
219	move	t1, a2
220
221	PTR_ADD	gp, s1			# adjust gp
222
223	/*
224	 * t0 = source address
225	 * t1 = target address
226	 * t2 = source end address
227	 */
2281:
229	PTR_L	t3, 0(t0)
230	PTR_S	t3, 0(t1)
231	PTR_ADDU t0, PTRSIZE
232	blt	t0, t2, 1b
233	 PTR_ADDU t1, PTRSIZE
234
235	/* If caches were enabled, we would have to flush them here. */
236	PTR_SUB	a1, t1, s2		# a1 <-- size
237	PTR_LA	t9, flush_cache
238	jalr	t9
239	 move	a0, s2			# a0 <-- destination address
240
241	/* Jump to where we've relocated ourselves */
242	PTR_ADDIU t0, s2, in_ram - _start
243	jr	t0
244	 nop
245
246	PTR	__rel_dyn_end
247	PTR	__rel_dyn_start
248	PTR	__image_copy_end
249	PTR	_GLOBAL_OFFSET_TABLE_
250	PTR	num_got_entries
251
252in_ram:
253	/*
254	 * Now we want to update GOT.
255	 *
256	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
257	 * generated by GNU ld. Skip these reserved entries from relocation.
258	 */
259	PTR_L	t3, -(1 * PTRSIZE)(t0)	# t3 <-- num_got_entries
260	PTR_L	t8, -(2 * PTRSIZE)(t0)	# t8 <-- _GLOBAL_OFFSET_TABLE_
261	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
262	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
263	PTR_LI	t2, 2
2641:
265	PTR_L	t1, 0(t8)
266	beqz	t1, 2f
267	 PTR_ADD t1, s1
268	PTR_S	t1, 0(t8)
2692:
270	PTR_ADDIU t2, 1
271	blt	t2, t3, 1b
272	 PTR_ADDIU t8, PTRSIZE
273
274	/* Update dynamic relocations */
275	PTR_L	t1, -(4 * PTRSIZE)(t0)	# t1 <-- __rel_dyn_start
276	PTR_L	t2, -(5 * PTRSIZE)(t0)	# t2 <-- __rel_dyn_end
277
278	b	2f			# skip first reserved entry
279	 PTR_ADDIU t1, 2 * PTRSIZE
280
2811:
282	lw	t8, -4(t1)		# t8 <-- relocation info
283
284	PTR_LI	t3, MIPS_RELOC
285	bne	t8, t3, 2f		# skip non-MIPS_RELOC entries
286	 nop
287
288	PTR_L	t3, -(2 * PTRSIZE)(t1)	# t3 <-- location to fix up in FLASH
289
290	PTR_L	t8, 0(t3)		# t8 <-- original pointer
291	PTR_ADD	t8, s1			# t8 <-- adjusted pointer
292
293	PTR_ADD	t3, s1			# t3 <-- location to fix up in RAM
294	PTR_S	t8, 0(t3)
295
2962:
297	blt	t1, t2, 1b
298	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
299
300	/*
301	 * Clear BSS
302	 *
303	 * GOT is now relocated. Thus __bss_start and __bss_end can be
304	 * accessed directly via $gp.
305	 */
306	PTR_LA	t1, __bss_start		# t1 <-- __bss_start
307	PTR_LA	t2, __bss_end		# t2 <-- __bss_end
308
3091:
310	PTR_S	zero, 0(t1)
311	blt	t1, t2, 1b
312	 PTR_ADDIU t1, PTRSIZE
313
314	move	a0, s0			# a0 <-- gd
315	move	a1, s2
316	PTR_LA	t9, board_init_r
317	jr	t9
318	 move	ra, zero
319
320	END(relocate_code)
321