xref: /openbmc/u-boot/arch/mips/cpu/start.S (revision 6645fd2c) 
1/*
2 *  Startup Code for MIPS32 CPU-core
3 *
4 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/asm.h>
12#include <asm/regdef.h>
13#include <asm/mipsregs.h>
14
15#ifndef CONFIG_SYS_INIT_SP_ADDR
16#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
17				CONFIG_SYS_INIT_SP_OFFSET)
18#endif
19
20#ifdef CONFIG_32BIT
21# define MIPS_RELOC	3
22# define STATUS_SET	0
23#endif
24
25#ifdef CONFIG_64BIT
26# ifdef CONFIG_SYS_LITTLE_ENDIAN
27#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
28	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
29# else
30#  define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
31	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
32# endif
33# define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
34# define STATUS_SET	ST0_KX
35#endif
36
37	/*
38	 * For the moment disable interrupts, mark the kernel mode and
39	 * set ST0_KX so that the CPU does not spit fire when using
40	 * 64-bit addresses.
41	 */
42	.macro	setup_c0_status set clr
43	.set	push
44	mfc0	t0, CP0_STATUS
45	or	t0, ST0_CU0 | \set | 0x1f | \clr
46	xor	t0, 0x1f | \clr
47	mtc0	t0, CP0_STATUS
48	.set	noreorder
49	sll	zero, 3				# ehb
50	.set	pop
51	.endm
52
53	.set noreorder
54
55ENTRY(_start)
56	/* U-Boot entry point */
57	b	reset
58	 nop
59
60	.org 0x10
61#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
62	/*
63	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
64	 * access external NOR flashes. If the board boots from NOR flash the
65	 * internal BootROM does a blind read at address 0xB0000010 to read the
66	 * initial configuration for that EBU in order to access the flash
67	 * device with correct parameters. This config option is board-specific.
68	 */
69	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
70	.word 0x0
71#elif defined(CONFIG_MALTA)
72	/*
73	 * Linux expects the Board ID here.
74	 */
75	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
76	.word 0x00000000
77#endif
78
79	.org 0x200
80	/* TLB refill, 32 bit task */
811:	b	1b
82	 nop
83
84	.org 0x280
85	/* XTLB refill, 64 bit task */
861:	b	1b
87	 nop
88
89	.org 0x300
90	/* Cache error exception */
911:	b	1b
92	 nop
93
94	.org 0x380
95	/* General exception */
961:	b	1b
97	 nop
98
99	.org 0x400
100	/* Catch interrupt exceptions */
1011:	b	1b
102	 nop
103
104	.org 0x480
105	/* EJTAG debug exception */
1061:	b	1b
107	 nop
108
109	.align 4
110reset:
111#if __mips_isa_rev >= 6
112	mfc0	t0, CP0_CONFIG, 5
113	and	t0, t0, MIPS_CONF5_VP
114	beqz	t0, 1f
115	 nop
116
117	b	2f
118	 mfc0	t0, CP0_GLOBALNUMBER
119#endif
120
1211:	mfc0	t0, CP0_EBASE
122	and	t0, t0, EBASE_CPUNUM
123
124	/* Hang if this isn't the first CPU in the system */
1252:	beqz	t0, 4f
126	 nop
1273:	wait
128	b	3b
129	 nop
130
131	/* Clear watch registers */
1324:	MTC0	zero, CP0_WATCHLO
133	mtc0	zero, CP0_WATCHHI
134
135	/* WP(Watch Pending), SW0/1 should be cleared */
136	mtc0	zero, CP0_CAUSE
137
138	setup_c0_status STATUS_SET 0
139
140	/* Init Timer */
141	mtc0	zero, CP0_COUNT
142	mtc0	zero, CP0_COMPARE
143
144#ifndef CONFIG_SKIP_LOWLEVEL_INIT
145	mfc0	t0, CP0_CONFIG
146	and	t0, t0, MIPS_CONF_IMPL
147	or	t0, t0, CONF_CM_UNCACHED
148	mtc0	t0, CP0_CONFIG
149	ehb
150#endif
151
152	/*
153	 * Initialize $gp, force pointer sized alignment of bal instruction to
154	 * forbid the compiler to put nop's between bal and _gp. This is
155	 * required to keep _gp and ra aligned to 8 byte.
156	 */
157	.align	PTRLOG
158	bal	1f
159	 nop
160	PTR	_gp
1611:
162	PTR_L	gp, 0(ra)
163
164#ifdef CONFIG_MIPS_CM
165	PTR_LA	t9, mips_cm_map
166	jalr	t9
167	 nop
168#endif
169
170#ifndef CONFIG_SKIP_LOWLEVEL_INIT
171# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
172	/* Initialize any external memory */
173	PTR_LA	t9, lowlevel_init
174	jalr	t9
175	 nop
176# endif
177
178	/* Initialize caches... */
179	PTR_LA	t9, mips_cache_reset
180	jalr	t9
181	 nop
182
183# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
184	/* Initialize any external memory */
185	PTR_LA	t9, lowlevel_init
186	jalr	t9
187	 nop
188# endif
189#endif
190
191	/* Set up temporary stack */
192	li	t0, -16
193	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
194	and	sp, t1, t0		# force 16 byte alignment
195	PTR_SUBU \
196		sp, sp, GD_SIZE		# reserve space for gd
197	and	sp, sp, t0		# force 16 byte alignment
198	move	k0, sp			# save gd pointer
199#ifdef CONFIG_SYS_MALLOC_F_LEN
200	li	t2, CONFIG_SYS_MALLOC_F_LEN
201	PTR_SUBU \
202		sp, sp, t2		# reserve space for early malloc
203	and	sp, sp, t0		# force 16 byte alignment
204#endif
205	move	fp, sp
206
207	/* Clear gd */
208	move	t0, k0
2091:
210	PTR_S	zero, 0(t0)
211	blt	t0, t1, 1b
212	 PTR_ADDIU t0, PTRSIZE
213
214#ifdef CONFIG_SYS_MALLOC_F_LEN
215	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
216#endif
217
218	move	a0, zero		# a0 <-- boot_flags = 0
219	PTR_LA	t9, board_init_f
220	jr	t9
221	 move	ra, zero
222
223	END(_start)
224
225/*
226 * void relocate_code (addr_sp, gd, addr_moni)
227 *
228 * This "function" does not return, instead it continues in RAM
229 * after relocating the monitor code.
230 *
231 * a0 = addr_sp
232 * a1 = gd
233 * a2 = destination address
234 */
235ENTRY(relocate_code)
236	move	sp, a0			# set new stack pointer
237	move	fp, sp
238
239	move	s0, a1			# save gd in s0
240	move	s2, a2			# save destination address in s2
241
242	PTR_LI	t0, CONFIG_SYS_MONITOR_BASE
243	PTR_SUB	s1, s2, t0		# s1 <-- relocation offset
244
245	PTR_LA	t2, __image_copy_end
246	move	t1, a2
247
248	/*
249	 * t0 = source address
250	 * t1 = target address
251	 * t2 = source end address
252	 */
2531:
254	PTR_L	t3, 0(t0)
255	PTR_S	t3, 0(t1)
256	PTR_ADDU t0, PTRSIZE
257	blt	t0, t2, 1b
258	 PTR_ADDU t1, PTRSIZE
259
260	/*
261	 * Now we want to update GOT.
262	 *
263	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
264	 * generated by GNU ld. Skip these reserved entries from relocation.
265	 */
266	PTR_LA	t3, num_got_entries
267	PTR_LA	t8, _GLOBAL_OFFSET_TABLE_
268	PTR_ADD	t8, s1			# t8 now holds relocated _G_O_T_
269	PTR_ADDIU t8, t8, 2 * PTRSIZE	# skipping first two entries
270	PTR_LI	t2, 2
2711:
272	PTR_L	t1, 0(t8)
273	beqz	t1, 2f
274	 PTR_ADD t1, s1
275	PTR_S	t1, 0(t8)
2762:
277	PTR_ADDIU t2, 1
278	blt	t2, t3, 1b
279	 PTR_ADDIU t8, PTRSIZE
280
281	/* Update dynamic relocations */
282	PTR_LA	t1, __rel_dyn_start
283	PTR_LA	t2, __rel_dyn_end
284
285	b	2f			# skip first reserved entry
286	 PTR_ADDIU t1, 2 * PTRSIZE
287
2881:
289	lw	t8, -4(t1)		# t8 <-- relocation info
290
291	PTR_LI	t3, MIPS_RELOC
292	bne	t8, t3, 2f		# skip non-MIPS_RELOC entries
293	 nop
294
295	PTR_L	t3, -(2 * PTRSIZE)(t1)	# t3 <-- location to fix up in FLASH
296
297	PTR_L	t8, 0(t3)		# t8 <-- original pointer
298	PTR_ADD	t8, s1			# t8 <-- adjusted pointer
299
300	PTR_ADD	t3, s1			# t3 <-- location to fix up in RAM
301	PTR_S	t8, 0(t3)
302
3032:
304	blt	t1, t2, 1b
305	 PTR_ADDIU t1, 2 * PTRSIZE	# each rel.dyn entry is 2*PTRSIZE bytes
306
307	/*
308	 * Flush caches to ensure our newly modified instructions are visible
309	 * to the instruction cache. We're still running with the old GOT, so
310	 * apply the reloc offset to the start address.
311	 */
312	PTR_LA	a0, __text_start
313	PTR_LA	a1, __text_end
314	PTR_SUB	a1, a1, a0
315	PTR_LA	t9, flush_cache
316	jalr	t9
317	 PTR_ADD	a0, s1
318
319	PTR_ADD	gp, s1			# adjust gp
320
321	/*
322	 * Clear BSS
323	 *
324	 * GOT is now relocated. Thus __bss_start and __bss_end can be
325	 * accessed directly via $gp.
326	 */
327	PTR_LA	t1, __bss_start		# t1 <-- __bss_start
328	PTR_LA	t2, __bss_end		# t2 <-- __bss_end
329
3301:
331	PTR_S	zero, 0(t1)
332	blt	t1, t2, 1b
333	 PTR_ADDIU t1, PTRSIZE
334
335	move	a0, s0			# a0 <-- gd
336	move	a1, s2
337	PTR_LA	t9, board_init_r
338	jr	t9
339	 move	ra, zero
340
341	END(relocate_code)
342