1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <command.h> 26 #include <netdev.h> 27 #include <asm/mipsregs.h> 28 #include <asm/cacheops.h> 29 #include <asm/reboot.h> 30 31 #define cache_op(op,addr) \ 32 __asm__ __volatile__( \ 33 " .set push \n" \ 34 " .set noreorder \n" \ 35 " .set mips3\n\t \n" \ 36 " cache %0, %1 \n" \ 37 " .set pop \n" \ 38 : \ 39 : "i" (op), "R" (*(unsigned char *)(addr))) 40 41 void __attribute__((weak)) _machine_restart(void) 42 { 43 } 44 45 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) 46 { 47 _machine_restart(); 48 49 fprintf(stderr, "*** reset failed ***\n"); 50 return 0; 51 } 52 53 void flush_cache(ulong start_addr, ulong size) 54 { 55 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; 56 unsigned long addr = start_addr & ~(lsize - 1); 57 unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); 58 59 while (1) { 60 cache_op(Hit_Writeback_Inv_D, addr); 61 cache_op(Hit_Invalidate_I, addr); 62 if (addr == aend) 63 break; 64 addr += lsize; 65 } 66 } 67 68 void flush_dcache_range(ulong start_addr, ulong stop) 69 { 70 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; 71 unsigned long addr = start_addr & ~(lsize - 1); 72 unsigned long aend = (stop - 1) & ~(lsize - 1); 73 74 while (1) { 75 cache_op(Hit_Writeback_Inv_D, addr); 76 if (addr == aend) 77 break; 78 addr += lsize; 79 } 80 } 81 82 void invalidate_dcache_range(ulong start_addr, ulong stop) 83 { 84 unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; 85 unsigned long addr = start_addr & ~(lsize - 1); 86 unsigned long aend = (stop - 1) & ~(lsize - 1); 87 88 while (1) { 89 cache_op(Hit_Invalidate_D, addr); 90 if (addr == aend) 91 break; 92 addr += lsize; 93 } 94 } 95 96 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) 97 { 98 write_c0_entrylo0(low0); 99 write_c0_pagemask(pagemask); 100 write_c0_entrylo1(low1); 101 write_c0_entryhi(hi); 102 write_c0_index(index); 103 tlb_write_indexed(); 104 } 105 106 int cpu_eth_init(bd_t *bis) 107 { 108 #ifdef CONFIG_SOC_AU1X00 109 au1x00_enet_initialize(bis); 110 #endif 111 return 0; 112 } 113