1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_INSERT_BOOT_CONFIG 32 select MIPS_L1_CACHE_SHIFT_6 33 select MIPS_L2_CACHE 34 select OF_CONTROL 35 select OF_ISA_BUS 36 select ROM_EXCEPTION_VECTORS 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SUPPORTS_CPU_MIPS32_R6 41 select SUPPORTS_CPU_MIPS64_R1 42 select SUPPORTS_CPU_MIPS64_R2 43 select SUPPORTS_CPU_MIPS64_R6 44 select SUPPORTS_LITTLE_ENDIAN 45 select SWAP_IO_SPACE 46 imply CMD_DM 47 48config TARGET_VCT 49 bool "Support vct" 50 select ROM_EXCEPTION_VECTORS 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_CPU_MIPS32_R1 53 select SUPPORTS_CPU_MIPS32_R2 54 select SYS_MIPS_CACHE_INIT_RAM_LOAD 55 56config ARCH_ATH79 57 bool "Support QCA/Atheros ath79" 58 select DM 59 select OF_CONTROL 60 imply CMD_DM 61 62config ARCH_BMIPS 63 bool "Support BMIPS SoCs" 64 select CLK 65 select CPU 66 select DM 67 select OF_CONTROL 68 select RAM 69 select SYSRESET 70 imply CMD_DM 71 72config ARCH_MT7620 73 bool "Support MT7620/7688 SoCs" 74 imply CMD_DM 75 select DISPLAY_CPUINFO 76 select DM 77 imply DM_ETH 78 imply DM_GPIO 79 select DM_SERIAL 80 imply DM_SPI 81 imply DM_SPI_FLASH 82 select ARCH_MISC_INIT if WATCHDOG 83 select MIPS_TUNE_24KC 84 select OF_CONTROL 85 select ROM_EXCEPTION_VECTORS 86 select SUPPORTS_CPU_MIPS32_R1 87 select SUPPORTS_CPU_MIPS32_R2 88 select SUPPORTS_LITTLE_ENDIAN 89 select SYSRESET 90 91config MACH_PIC32 92 bool "Support Microchip PIC32" 93 select DM 94 select OF_CONTROL 95 imply CMD_DM 96 97config TARGET_BOSTON 98 bool "Support Boston" 99 select DM 100 select DM_SERIAL 101 select MIPS_CM 102 select MIPS_L1_CACHE_SHIFT_6 103 select MIPS_L2_CACHE 104 select OF_BOARD_SETUP 105 select OF_CONTROL 106 select ROM_EXCEPTION_VECTORS 107 select SUPPORTS_BIG_ENDIAN 108 select SUPPORTS_CPU_MIPS32_R1 109 select SUPPORTS_CPU_MIPS32_R2 110 select SUPPORTS_CPU_MIPS32_R6 111 select SUPPORTS_CPU_MIPS64_R1 112 select SUPPORTS_CPU_MIPS64_R2 113 select SUPPORTS_CPU_MIPS64_R6 114 select SUPPORTS_LITTLE_ENDIAN 115 imply CMD_DM 116 117config TARGET_XILFPGA 118 bool "Support Imagination Xilfpga" 119 select DM 120 select DM_ETH 121 select DM_GPIO 122 select DM_SERIAL 123 select MIPS_L1_CACHE_SHIFT_4 124 select OF_CONTROL 125 select ROM_EXCEPTION_VECTORS 126 select SUPPORTS_CPU_MIPS32_R1 127 select SUPPORTS_CPU_MIPS32_R2 128 select SUPPORTS_LITTLE_ENDIAN 129 imply CMD_DM 130 help 131 This supports IMGTEC MIPSfpga platform 132 133endchoice 134 135source "board/imgtec/boston/Kconfig" 136source "board/imgtec/malta/Kconfig" 137source "board/imgtec/xilfpga/Kconfig" 138source "board/micronas/vct/Kconfig" 139source "board/qemu-mips/Kconfig" 140source "arch/mips/mach-ath79/Kconfig" 141source "arch/mips/mach-bmips/Kconfig" 142source "arch/mips/mach-pic32/Kconfig" 143source "arch/mips/mach-mt7620/Kconfig" 144 145if MIPS 146 147choice 148 prompt "Endianness selection" 149 help 150 Some MIPS boards can be configured for either little or big endian 151 byte order. These modes require different U-Boot images. In general there 152 is one preferred byteorder for a particular system but some systems are 153 just as commonly used in the one or the other endianness. 154 155config SYS_BIG_ENDIAN 156 bool "Big endian" 157 depends on SUPPORTS_BIG_ENDIAN 158 159config SYS_LITTLE_ENDIAN 160 bool "Little endian" 161 depends on SUPPORTS_LITTLE_ENDIAN 162 163endchoice 164 165choice 166 prompt "CPU selection" 167 default CPU_MIPS32_R2 168 169config CPU_MIPS32_R1 170 bool "MIPS32 Release 1" 171 depends on SUPPORTS_CPU_MIPS32_R1 172 select 32BIT 173 help 174 Choose this option to build an U-Boot for release 1 through 5 of the 175 MIPS32 architecture. 176 177config CPU_MIPS32_R2 178 bool "MIPS32 Release 2" 179 depends on SUPPORTS_CPU_MIPS32_R2 180 select 32BIT 181 help 182 Choose this option to build an U-Boot for release 2 through 5 of the 183 MIPS32 architecture. 184 185config CPU_MIPS32_R6 186 bool "MIPS32 Release 6" 187 depends on SUPPORTS_CPU_MIPS32_R6 188 select 32BIT 189 help 190 Choose this option to build an U-Boot for release 6 or later of the 191 MIPS32 architecture. 192 193config CPU_MIPS64_R1 194 bool "MIPS64 Release 1" 195 depends on SUPPORTS_CPU_MIPS64_R1 196 select 64BIT 197 help 198 Choose this option to build a kernel for release 1 through 5 of the 199 MIPS64 architecture. 200 201config CPU_MIPS64_R2 202 bool "MIPS64 Release 2" 203 depends on SUPPORTS_CPU_MIPS64_R2 204 select 64BIT 205 help 206 Choose this option to build a kernel for release 2 through 5 of the 207 MIPS64 architecture. 208 209config CPU_MIPS64_R6 210 bool "MIPS64 Release 6" 211 depends on SUPPORTS_CPU_MIPS64_R6 212 select 64BIT 213 help 214 Choose this option to build a kernel for release 6 or later of the 215 MIPS64 architecture. 216 217endchoice 218 219menu "General setup" 220 221config ROM_EXCEPTION_VECTORS 222 bool "Build U-Boot image with exception vectors" 223 help 224 Enable this to include exception vectors in the U-Boot image. This is 225 required if the U-Boot entry point is equal to the address of the 226 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 227 U-Boot booted from parallel NOR flash). 228 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 229 In that case the image size will be reduced by 0x500 bytes. 230 231config MIPS_CM_BASE 232 hex "MIPS CM GCR Base Address" 233 depends on MIPS_CM 234 default 0x16100000 if TARGET_BOSTON 235 default 0x1fbf8000 236 help 237 The physical base address at which to map the MIPS Coherence Manager 238 Global Configuration Registers (GCRs). This should be set such that 239 the GCRs occupy a region of the physical address space which is 240 otherwise unused, or at minimum that software doesn't need to access. 241 242config MIPS_CACHE_INDEX_BASE 243 hex "Index base address for cache initialisation" 244 default 0x80000000 if CPU_MIPS32 245 default 0xffffffff80000000 if CPU_MIPS64 246 help 247 This is the base address for a memory block, which is used for 248 initialising the cache lines. This is also the base address of a memory 249 block which is used for loading and filling cache lines when 250 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 251 Normally this is CKSEG0. If the MIPS system needs to move this block 252 to some SRAM or ScratchPad RAM, adapt this option accordingly. 253 254config MIPS_RELOCATION_TABLE_SIZE 255 hex "Relocation table size" 256 range 0x100 0x10000 257 default "0x8000" 258 ---help--- 259 A table of relocation data will be appended to the U-Boot binary 260 and parsed in relocate_code() to fix up all offsets in the relocated 261 U-Boot. 262 263 This option allows the amount of space reserved for the table to be 264 adjusted in a range from 256 up to 64k. The default is 32k and should 265 be ok in most cases. Reduce this value to shrink the size of U-Boot 266 binary. 267 268 The build will fail and a valid size suggested if this is too small. 269 270 If unsure, leave at the default value. 271 272endmenu 273 274menu "OS boot interface" 275 276config MIPS_BOOT_CMDLINE_LEGACY 277 bool "Hand over legacy command line to Linux kernel" 278 default y 279 help 280 Enable this option if you want U-Boot to hand over the Yamon-style 281 command line to the kernel. All bootargs will be prepared as argc/argv 282 compatible list. The argument count (argc) is stored in register $a0. 283 The address of the argument list (argv) is stored in register $a1. 284 285config MIPS_BOOT_ENV_LEGACY 286 bool "Hand over legacy environment to Linux kernel" 287 default y 288 help 289 Enable this option if you want U-Boot to hand over the Yamon-style 290 environment to the kernel. Information like memory size, initrd 291 address and size will be prepared as zero-terminated key/value list. 292 The address of the environment is stored in register $a2. 293 294config MIPS_BOOT_FDT 295 bool "Hand over a flattened device tree to Linux kernel" 296 default n 297 help 298 Enable this option if you want U-Boot to hand over a flattened 299 device tree to the kernel. According to UHI register $a0 will be set 300 to -2 and the FDT address is stored in $a1. 301 302endmenu 303 304config SUPPORTS_BIG_ENDIAN 305 bool 306 307config SUPPORTS_LITTLE_ENDIAN 308 bool 309 310config SUPPORTS_CPU_MIPS32_R1 311 bool 312 313config SUPPORTS_CPU_MIPS32_R2 314 bool 315 316config SUPPORTS_CPU_MIPS32_R6 317 bool 318 319config SUPPORTS_CPU_MIPS64_R1 320 bool 321 322config SUPPORTS_CPU_MIPS64_R2 323 bool 324 325config SUPPORTS_CPU_MIPS64_R6 326 bool 327 328config CPU_MIPS32 329 bool 330 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 331 332config CPU_MIPS64 333 bool 334 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 335 336config MIPS_TUNE_4KC 337 bool 338 339config MIPS_TUNE_14KC 340 bool 341 342config MIPS_TUNE_24KC 343 bool 344 345config MIPS_TUNE_34KC 346 bool 347 348config MIPS_TUNE_74KC 349 bool 350 351config 32BIT 352 bool 353 354config 64BIT 355 bool 356 357config SWAP_IO_SPACE 358 bool 359 360config SYS_MIPS_CACHE_INIT_RAM_LOAD 361 bool 362 363config MIPS_INIT_STACK_IN_SRAM 364 bool 365 default n 366 help 367 Select this if the initial stack frame could be setup in SRAM. 368 Normally the initial stack frame is set up in DRAM which is often 369 only available after lowlevel_init. With this option the initial 370 stack frame and the early C environment is set up before 371 lowlevel_init. Thus lowlevel_init does not need to be implemented 372 in assembler. 373 374config SYS_DCACHE_SIZE 375 int 376 default 0 377 help 378 The total size of the L1 Dcache, if known at compile time. 379 380config SYS_DCACHE_LINE_SIZE 381 int 382 default 0 383 help 384 The size of L1 Dcache lines, if known at compile time. 385 386config SYS_ICACHE_SIZE 387 int 388 default 0 389 help 390 The total size of the L1 ICache, if known at compile time. 391 392config SYS_ICACHE_LINE_SIZE 393 int 394 default 0 395 help 396 The size of L1 Icache lines, if known at compile time. 397 398config SYS_CACHE_SIZE_AUTO 399 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 400 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 401 help 402 Select this (or let it be auto-selected by not defining any cache 403 sizes) in order to allow U-Boot to automatically detect the sizes 404 of caches at runtime. This has a small cost in code size & runtime 405 so if you know the cache configuration for your system at compile 406 time it would be beneficial to configure it. 407 408config MIPS_L1_CACHE_SHIFT_4 409 bool 410 411config MIPS_L1_CACHE_SHIFT_5 412 bool 413 414config MIPS_L1_CACHE_SHIFT_6 415 bool 416 417config MIPS_L1_CACHE_SHIFT_7 418 bool 419 420config MIPS_L1_CACHE_SHIFT 421 int 422 default "7" if MIPS_L1_CACHE_SHIFT_7 423 default "6" if MIPS_L1_CACHE_SHIFT_6 424 default "5" if MIPS_L1_CACHE_SHIFT_5 425 default "4" if MIPS_L1_CACHE_SHIFT_4 426 default "5" 427 428config MIPS_L2_CACHE 429 bool 430 help 431 Select this if your system includes an L2 cache and you want U-Boot 432 to initialise & maintain it. 433 434config DYNAMIC_IO_PORT_BASE 435 bool 436 437config MIPS_CM 438 bool 439 help 440 Select this if your system contains a MIPS Coherence Manager and you 441 wish U-Boot to configure it or make use of it to retrieve system 442 information such as cache configuration. 443 444config MIPS_INSERT_BOOT_CONFIG 445 bool 446 default n 447 help 448 Enable this to insert some board-specific boot configuration in 449 the U-Boot binary at offset 0x10. 450 451config MIPS_BOOT_CONFIG_WORD0 452 hex 453 depends on MIPS_INSERT_BOOT_CONFIG 454 default 0x420 if TARGET_MALTA 455 default 0x0 456 help 457 Value which is inserted as boot config word 0. 458 459config MIPS_BOOT_CONFIG_WORD1 460 hex 461 depends on MIPS_INSERT_BOOT_CONFIG 462 default 0x0 463 help 464 Value which is inserted as boot config word 1. 465 466endif 467 468endmenu 469