1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __MICROBLAZE_CACHE_H__
8 #define __MICROBLAZE_CACHE_H__
9 
10 /*
11  * The microblaze can have either a 4 or 16 byte cacheline depending on whether
12  * you are using OPB(4) or CacheLink(16).  If the board config has not specified
13  * a cacheline size we assume the larger value of 16 bytes for DMA buffer
14  * alignment.
15  */
16 #ifdef CONFIG_SYS_CACHELINE_SIZE
17 #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
18 #else
19 #define ARCH_DMA_MINALIGN	16
20 #endif
21 
22 #endif /* __MICROBLAZE_CACHE_H__ */
23