1 /*
2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  *
6  * Intel Quark MRC bindings include several properties
7  * as part of an Intel Quark MRC node. In most cases,
8  * the value of these properties uses the standard values
9  * defined in this header.
10  */
11 
12 #ifndef _DT_BINDINGS_QRK_MRC_H_
13 #define _DT_BINDINGS_QRK_MRC_H_
14 
15 /* MRC platform data flags */
16 #define MRC_FLAG_ECC_EN		0x00000001
17 #define MRC_FLAG_SCRAMBLE_EN	0x00000002
18 #define MRC_FLAG_MEMTEST_EN	0x00000004
19 /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
20 #define MRC_FLAG_TOP_TREE_EN	0x00000008
21 /* If set ODR signal is asserted to DRAM devices on writes */
22 #define MRC_FLAG_WR_ODT_EN	0x00000010
23 
24 /* DRAM width */
25 #define DRAM_WIDTH_X8		0
26 #define DRAM_WIDTH_X16		1
27 #define DRAM_WIDTH_X32		2
28 
29 /* DRAM speed */
30 #define DRAM_FREQ_800		0
31 #define DRAM_FREQ_1066		1
32 
33 /* DRAM type */
34 #define DRAM_TYPE_DDR3		0
35 #define DRAM_TYPE_DDR3L		1
36 
37 /* DRAM rank mask */
38 #define DRAM_RANK(n)		(1 << (n))
39 
40 /* DRAM channel mask */
41 #define DRAM_CHANNEL(n)		(1 << (n))
42 
43 /* DRAM channel width */
44 #define DRAM_CHANNEL_WIDTH_X8	0
45 #define DRAM_CHANNEL_WIDTH_X16	1
46 #define DRAM_CHANNEL_WIDTH_X32	2
47 
48 /* DRAM address mode */
49 #define DRAM_ADDR_MODE0		0
50 #define DRAM_ADDR_MODE1		1
51 #define DRAM_ADDR_MODE2		2
52 
53 /* DRAM refresh rate */
54 #define DRAM_REFRESH_RATE_195US	1
55 #define DRAM_REFRESH_RATE_39US	2
56 #define DRAM_REFRESH_RATE_785US	3
57 
58 /* DRAM SR temprature range */
59 #define DRAM_SRT_RANGE_NORMAL	0
60 #define DRAM_SRT_RANGE_EXTENDED	1
61 
62 /* DRAM ron value */
63 #define DRAM_RON_34OHM		0
64 #define DRAM_RON_40OHM		1
65 
66 /* DRAM rtt nom value */
67 #define DRAM_RTT_NOM_40OHM	0
68 #define DRAM_RTT_NOM_60OHM	1
69 #define DRAM_RTT_NOM_120OHM	2
70 
71 /* DRAM rd odt value */
72 #define DRAM_RD_ODT_OFF		0
73 #define DRAM_RD_ODT_60OHM	1
74 #define DRAM_RD_ODT_120OHM	2
75 #define DRAM_RD_ODT_180OHM	3
76 
77 /* DRAM density */
78 #define DRAM_DENSITY_512M	0
79 #define DRAM_DENSITY_1G		1
80 #define DRAM_DENSITY_2G		2
81 #define DRAM_DENSITY_4G		3
82 
83 #endif /* _DT_BINDINGS_QRK_MRC_H_ */
84