1*b1420c81SBin Meng /* 2*b1420c81SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*b1420c81SBin Meng * 4*b1420c81SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*b1420c81SBin Meng * 6*b1420c81SBin Meng * Intel Quark MRC bindings include several properties 7*b1420c81SBin Meng * as part of an Intel Quark MRC node. In most cases, 8*b1420c81SBin Meng * the value of these properties uses the standard values 9*b1420c81SBin Meng * defined in this header. 10*b1420c81SBin Meng */ 11*b1420c81SBin Meng 12*b1420c81SBin Meng #ifndef _DT_BINDINGS_QRK_MRC_H_ 13*b1420c81SBin Meng #define _DT_BINDINGS_QRK_MRC_H_ 14*b1420c81SBin Meng 15*b1420c81SBin Meng /* MRC platform data flags */ 16*b1420c81SBin Meng #define MRC_FLAG_ECC_EN 0x00000001 17*b1420c81SBin Meng #define MRC_FLAG_SCRAMBLE_EN 0x00000002 18*b1420c81SBin Meng #define MRC_FLAG_MEMTEST_EN 0x00000004 19*b1420c81SBin Meng /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ 20*b1420c81SBin Meng #define MRC_FLAG_TOP_TREE_EN 0x00000008 21*b1420c81SBin Meng /* If set ODR signal is asserted to DRAM devices on writes */ 22*b1420c81SBin Meng #define MRC_FLAG_WR_ODT_EN 0x00000010 23*b1420c81SBin Meng 24*b1420c81SBin Meng /* DRAM width */ 25*b1420c81SBin Meng #define DRAM_WIDTH_X8 0 26*b1420c81SBin Meng #define DRAM_WIDTH_X16 1 27*b1420c81SBin Meng #define DRAM_WIDTH_X32 2 28*b1420c81SBin Meng 29*b1420c81SBin Meng /* DRAM speed */ 30*b1420c81SBin Meng #define DRAM_FREQ_800 0 31*b1420c81SBin Meng #define DRAM_FREQ_1066 1 32*b1420c81SBin Meng 33*b1420c81SBin Meng /* DRAM type */ 34*b1420c81SBin Meng #define DRAM_TYPE_DDR3 0 35*b1420c81SBin Meng #define DRAM_TYPE_DDR3L 1 36*b1420c81SBin Meng 37*b1420c81SBin Meng /* DRAM rank mask */ 38*b1420c81SBin Meng #define DRAM_RANK(n) (1 << (n)) 39*b1420c81SBin Meng 40*b1420c81SBin Meng /* DRAM channel mask */ 41*b1420c81SBin Meng #define DRAM_CHANNEL(n) (1 << (n)) 42*b1420c81SBin Meng 43*b1420c81SBin Meng /* DRAM channel width */ 44*b1420c81SBin Meng #define DRAM_CHANNEL_WIDTH_X8 0 45*b1420c81SBin Meng #define DRAM_CHANNEL_WIDTH_X16 1 46*b1420c81SBin Meng #define DRAM_CHANNEL_WIDTH_X32 2 47*b1420c81SBin Meng 48*b1420c81SBin Meng /* DRAM address mode */ 49*b1420c81SBin Meng #define DRAM_ADDR_MODE0 0 50*b1420c81SBin Meng #define DRAM_ADDR_MODE1 1 51*b1420c81SBin Meng #define DRAM_ADDR_MODE2 2 52*b1420c81SBin Meng 53*b1420c81SBin Meng /* DRAM refresh rate */ 54*b1420c81SBin Meng #define DRAM_REFRESH_RATE_195US 1 55*b1420c81SBin Meng #define DRAM_REFRESH_RATE_39US 2 56*b1420c81SBin Meng #define DRAM_REFRESH_RATE_785US 3 57*b1420c81SBin Meng 58*b1420c81SBin Meng /* DRAM SR temprature range */ 59*b1420c81SBin Meng #define DRAM_SRT_RANGE_NORMAL 0 60*b1420c81SBin Meng #define DRAM_SRT_RANGE_EXTENDED 1 61*b1420c81SBin Meng 62*b1420c81SBin Meng /* DRAM ron value */ 63*b1420c81SBin Meng #define DRAM_RON_34OHM 0 64*b1420c81SBin Meng #define DRAM_RON_40OHM 1 65*b1420c81SBin Meng 66*b1420c81SBin Meng /* DRAM rtt nom value */ 67*b1420c81SBin Meng #define DRAM_RTT_NOM_40OHM 0 68*b1420c81SBin Meng #define DRAM_RTT_NOM_60OHM 1 69*b1420c81SBin Meng #define DRAM_RTT_NOM_120OHM 2 70*b1420c81SBin Meng 71*b1420c81SBin Meng /* DRAM rd odt value */ 72*b1420c81SBin Meng #define DRAM_RD_ODT_OFF 0 73*b1420c81SBin Meng #define DRAM_RD_ODT_60OHM 1 74*b1420c81SBin Meng #define DRAM_RD_ODT_120OHM 2 75*b1420c81SBin Meng #define DRAM_RD_ODT_180OHM 3 76*b1420c81SBin Meng 77*b1420c81SBin Meng /* DRAM density */ 78*b1420c81SBin Meng #define DRAM_DENSITY_512M 0 79*b1420c81SBin Meng #define DRAM_DENSITY_1G 1 80*b1420c81SBin Meng #define DRAM_DENSITY_2G 2 81*b1420c81SBin Meng #define DRAM_DENSITY_4G 3 82*b1420c81SBin Meng 83*b1420c81SBin Meng #endif /* _DT_BINDINGS_QRK_MRC_H_ */ 84