1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b1420c81SBin Meng /* 3b1420c81SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4b1420c81SBin Meng * 5b1420c81SBin Meng * Intel Quark MRC bindings include several properties 6b1420c81SBin Meng * as part of an Intel Quark MRC node. In most cases, 7b1420c81SBin Meng * the value of these properties uses the standard values 8b1420c81SBin Meng * defined in this header. 9b1420c81SBin Meng */ 10b1420c81SBin Meng 11b1420c81SBin Meng #ifndef _DT_BINDINGS_QRK_MRC_H_ 12b1420c81SBin Meng #define _DT_BINDINGS_QRK_MRC_H_ 13b1420c81SBin Meng 14b1420c81SBin Meng /* MRC platform data flags */ 15b1420c81SBin Meng #define MRC_FLAG_ECC_EN 0x00000001 16b1420c81SBin Meng #define MRC_FLAG_SCRAMBLE_EN 0x00000002 17b1420c81SBin Meng #define MRC_FLAG_MEMTEST_EN 0x00000004 18b1420c81SBin Meng /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ 19b1420c81SBin Meng #define MRC_FLAG_TOP_TREE_EN 0x00000008 20b1420c81SBin Meng /* If set ODR signal is asserted to DRAM devices on writes */ 21b1420c81SBin Meng #define MRC_FLAG_WR_ODT_EN 0x00000010 22b1420c81SBin Meng 23b1420c81SBin Meng /* DRAM width */ 24b1420c81SBin Meng #define DRAM_WIDTH_X8 0 25b1420c81SBin Meng #define DRAM_WIDTH_X16 1 26b1420c81SBin Meng #define DRAM_WIDTH_X32 2 27b1420c81SBin Meng 28b1420c81SBin Meng /* DRAM speed */ 29b1420c81SBin Meng #define DRAM_FREQ_800 0 30b1420c81SBin Meng #define DRAM_FREQ_1066 1 31b1420c81SBin Meng 32b1420c81SBin Meng /* DRAM type */ 33b1420c81SBin Meng #define DRAM_TYPE_DDR3 0 34b1420c81SBin Meng #define DRAM_TYPE_DDR3L 1 35b1420c81SBin Meng 36b1420c81SBin Meng /* DRAM rank mask */ 37b1420c81SBin Meng #define DRAM_RANK(n) (1 << (n)) 38b1420c81SBin Meng 39b1420c81SBin Meng /* DRAM channel mask */ 40b1420c81SBin Meng #define DRAM_CHANNEL(n) (1 << (n)) 41b1420c81SBin Meng 42b1420c81SBin Meng /* DRAM channel width */ 43b1420c81SBin Meng #define DRAM_CHANNEL_WIDTH_X8 0 44b1420c81SBin Meng #define DRAM_CHANNEL_WIDTH_X16 1 45b1420c81SBin Meng #define DRAM_CHANNEL_WIDTH_X32 2 46b1420c81SBin Meng 47b1420c81SBin Meng /* DRAM address mode */ 48b1420c81SBin Meng #define DRAM_ADDR_MODE0 0 49b1420c81SBin Meng #define DRAM_ADDR_MODE1 1 50b1420c81SBin Meng #define DRAM_ADDR_MODE2 2 51b1420c81SBin Meng 52b1420c81SBin Meng /* DRAM refresh rate */ 53b1420c81SBin Meng #define DRAM_REFRESH_RATE_195US 1 54b1420c81SBin Meng #define DRAM_REFRESH_RATE_39US 2 55b1420c81SBin Meng #define DRAM_REFRESH_RATE_785US 3 56b1420c81SBin Meng 57b1420c81SBin Meng /* DRAM SR temprature range */ 58b1420c81SBin Meng #define DRAM_SRT_RANGE_NORMAL 0 59b1420c81SBin Meng #define DRAM_SRT_RANGE_EXTENDED 1 60b1420c81SBin Meng 61b1420c81SBin Meng /* DRAM ron value */ 62b1420c81SBin Meng #define DRAM_RON_34OHM 0 63b1420c81SBin Meng #define DRAM_RON_40OHM 1 64b1420c81SBin Meng 65b1420c81SBin Meng /* DRAM rtt nom value */ 66b1420c81SBin Meng #define DRAM_RTT_NOM_40OHM 0 67b1420c81SBin Meng #define DRAM_RTT_NOM_60OHM 1 68b1420c81SBin Meng #define DRAM_RTT_NOM_120OHM 2 69b1420c81SBin Meng 70b1420c81SBin Meng /* DRAM rd odt value */ 71b1420c81SBin Meng #define DRAM_RD_ODT_OFF 0 72b1420c81SBin Meng #define DRAM_RD_ODT_60OHM 1 73b1420c81SBin Meng #define DRAM_RD_ODT_120OHM 2 74b1420c81SBin Meng #define DRAM_RD_ODT_180OHM 3 75b1420c81SBin Meng 76b1420c81SBin Meng /* DRAM density */ 77b1420c81SBin Meng #define DRAM_DENSITY_512M 0 78b1420c81SBin Meng #define DRAM_DENSITY_1G 1 79b1420c81SBin Meng #define DRAM_DENSITY_2G 2 80b1420c81SBin Meng #define DRAM_DENSITY_4G 3 81b1420c81SBin Meng 82b1420c81SBin Meng #endif /* _DT_BINDINGS_QRK_MRC_H_ */ 83