1*bae2f282SAndy Yan /*
2*bae2f282SAndy Yan  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3*bae2f282SAndy Yan  * Author: Shawn Lin <shawn.lin@rock-chips.com>
4*bae2f282SAndy Yan  * SPDX-License-Identifier:     GPL-2.0+
5*bae2f282SAndy Yan  */
6*bae2f282SAndy Yan 
7*bae2f282SAndy Yan #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
8*bae2f282SAndy Yan #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
9*bae2f282SAndy Yan 
10*bae2f282SAndy Yan /* pll id */
11*bae2f282SAndy Yan #define PLL_APLL			0
12*bae2f282SAndy Yan #define PLL_DPLL			1
13*bae2f282SAndy Yan #define PLL_GPLL			2
14*bae2f282SAndy Yan #define ARMCLK				3
15*bae2f282SAndy Yan 
16*bae2f282SAndy Yan /* sclk gates (special clocks) */
17*bae2f282SAndy Yan #define SCLK_MAC			64
18*bae2f282SAndy Yan #define SCLK_SPI0			65
19*bae2f282SAndy Yan #define SCLK_NANDC			67
20*bae2f282SAndy Yan #define SCLK_SDMMC			68
21*bae2f282SAndy Yan #define SCLK_SDIO			69
22*bae2f282SAndy Yan #define SCLK_EMMC			71
23*bae2f282SAndy Yan #define SCLK_UART0			72
24*bae2f282SAndy Yan #define SCLK_UART1			73
25*bae2f282SAndy Yan #define SCLK_UART2			74
26*bae2f282SAndy Yan #define SCLK_I2S0			75
27*bae2f282SAndy Yan #define SCLK_I2S1			76
28*bae2f282SAndy Yan #define SCLK_I2S2			77
29*bae2f282SAndy Yan #define SCLK_TIMER0			78
30*bae2f282SAndy Yan #define SCLK_TIMER1			79
31*bae2f282SAndy Yan #define SCLK_SFC			80
32*bae2f282SAndy Yan #define SCLK_SDMMC_DRV			81
33*bae2f282SAndy Yan #define SCLK_SDIO_DRV			82
34*bae2f282SAndy Yan #define SCLK_EMMC_DRV			83
35*bae2f282SAndy Yan #define SCLK_SDMMC_SAMPLE		84
36*bae2f282SAndy Yan #define SCLK_SDIO_SAMPLE		85
37*bae2f282SAndy Yan #define SCLK_EMMC_SAMPLE		86
38*bae2f282SAndy Yan #define SCLK_MAC_RX			87
39*bae2f282SAndy Yan #define SCLK_MAC_TX			88
40*bae2f282SAndy Yan #define SCLK_MACREF			89
41*bae2f282SAndy Yan #define SCLK_MACREF_OUT			90
42*bae2f282SAndy Yan 
43*bae2f282SAndy Yan 
44*bae2f282SAndy Yan /* aclk gates */
45*bae2f282SAndy Yan #define ACLK_DMAC			192
46*bae2f282SAndy Yan #define ACLK_PRE			193
47*bae2f282SAndy Yan #define ACLK_CORE			194
48*bae2f282SAndy Yan #define ACLK_ENMCORE			195
49*bae2f282SAndy Yan #define ACLK_GMAC			196
50*bae2f282SAndy Yan 
51*bae2f282SAndy Yan 
52*bae2f282SAndy Yan /* pclk gates */
53*bae2f282SAndy Yan #define PCLK_GPIO1			256
54*bae2f282SAndy Yan #define PCLK_GPIO2			257
55*bae2f282SAndy Yan #define PCLK_GPIO3			258
56*bae2f282SAndy Yan #define PCLK_GRF			259
57*bae2f282SAndy Yan #define PCLK_I2C1			260
58*bae2f282SAndy Yan #define PCLK_I2C2			261
59*bae2f282SAndy Yan #define PCLK_I2C3			262
60*bae2f282SAndy Yan #define PCLK_SPI			263
61*bae2f282SAndy Yan #define PCLK_SFC			264
62*bae2f282SAndy Yan #define PCLK_UART0			265
63*bae2f282SAndy Yan #define PCLK_UART1			266
64*bae2f282SAndy Yan #define PCLK_UART2			267
65*bae2f282SAndy Yan #define PCLK_TSADC			268
66*bae2f282SAndy Yan #define PCLK_PWM			269
67*bae2f282SAndy Yan #define PCLK_TIMER			270
68*bae2f282SAndy Yan #define PCLK_PERI			271
69*bae2f282SAndy Yan #define PCLK_GMAC			272
70*bae2f282SAndy Yan 
71*bae2f282SAndy Yan /* hclk gates */
72*bae2f282SAndy Yan #define HCLK_I2S0_8CH			320
73*bae2f282SAndy Yan #define HCLK_I2S1_8CH			321
74*bae2f282SAndy Yan #define HCLK_I2S2_2CH			322
75*bae2f282SAndy Yan #define HCLK_NANDC			323
76*bae2f282SAndy Yan #define HCLK_SDMMC			324
77*bae2f282SAndy Yan #define HCLK_SDIO			325
78*bae2f282SAndy Yan #define HCLK_EMMC			326
79*bae2f282SAndy Yan #define HCLK_PERI			327
80*bae2f282SAndy Yan #define HCLK_SFC			328
81*bae2f282SAndy Yan 
82*bae2f282SAndy Yan #define CLK_NR_CLKS			(HCLK_SFC + 1)
83*bae2f282SAndy Yan 
84*bae2f282SAndy Yan /* reset id */
85*bae2f282SAndy Yan #define SRST_CORE_PO_AD		0
86*bae2f282SAndy Yan #define SRST_CORE_AD			1
87*bae2f282SAndy Yan #define SRST_L2_AD			2
88*bae2f282SAndy Yan #define SRST_CPU_NIU_AD		3
89*bae2f282SAndy Yan #define SRST_CORE_PO			4
90*bae2f282SAndy Yan #define SRST_CORE			5
91*bae2f282SAndy Yan #define SRST_L2			6
92*bae2f282SAndy Yan #define SRST_CORE_DBG			8
93*bae2f282SAndy Yan #define PRST_DBG			9
94*bae2f282SAndy Yan #define RST_DAP			10
95*bae2f282SAndy Yan #define PRST_DBG_NIU			11
96*bae2f282SAndy Yan #define ARST_STRC_SYS_AD		15
97*bae2f282SAndy Yan 
98*bae2f282SAndy Yan #define SRST_DDRPHY_CLKDIV		16
99*bae2f282SAndy Yan #define SRST_DDRPHY			17
100*bae2f282SAndy Yan #define PRST_DDRPHY			18
101*bae2f282SAndy Yan #define PRST_HDMIPHY			19
102*bae2f282SAndy Yan #define PRST_VDACPHY			20
103*bae2f282SAndy Yan #define PRST_VADCPHY			21
104*bae2f282SAndy Yan #define PRST_MIPI_CSI_PHY		22
105*bae2f282SAndy Yan #define PRST_MIPI_DSI_PHY		23
106*bae2f282SAndy Yan #define PRST_ACODEC			24
107*bae2f282SAndy Yan #define ARST_BUS_NIU			25
108*bae2f282SAndy Yan #define PRST_TOP_NIU			26
109*bae2f282SAndy Yan #define ARST_INTMEM			27
110*bae2f282SAndy Yan #define HRST_ROM			28
111*bae2f282SAndy Yan #define ARST_DMAC			29
112*bae2f282SAndy Yan #define SRST_MSCH_NIU			30
113*bae2f282SAndy Yan #define PRST_MSCH_NIU			31
114*bae2f282SAndy Yan 
115*bae2f282SAndy Yan #define PRST_DDRUPCTL			32
116*bae2f282SAndy Yan #define NRST_DDRUPCTL			33
117*bae2f282SAndy Yan #define PRST_DDRMON			34
118*bae2f282SAndy Yan #define HRST_I2S0_8CH			35
119*bae2f282SAndy Yan #define MRST_I2S0_8CH			36
120*bae2f282SAndy Yan #define HRST_I2S1_2CH			37
121*bae2f282SAndy Yan #define MRST_IS21_2CH			38
122*bae2f282SAndy Yan #define HRST_I2S2_2CH			39
123*bae2f282SAndy Yan #define MRST_I2S2_2CH			40
124*bae2f282SAndy Yan #define HRST_CRYPTO			41
125*bae2f282SAndy Yan #define SRST_CRYPTO			42
126*bae2f282SAndy Yan #define PRST_SPI			43
127*bae2f282SAndy Yan #define SRST_SPI			44
128*bae2f282SAndy Yan #define PRST_UART0			45
129*bae2f282SAndy Yan #define PRST_UART1			46
130*bae2f282SAndy Yan #define PRST_UART2			47
131*bae2f282SAndy Yan 
132*bae2f282SAndy Yan #define SRST_UART0			48
133*bae2f282SAndy Yan #define SRST_UART1			49
134*bae2f282SAndy Yan #define SRST_UART2			50
135*bae2f282SAndy Yan #define PRST_I2C1			51
136*bae2f282SAndy Yan #define PRST_I2C2			52
137*bae2f282SAndy Yan #define PRST_I2C3			53
138*bae2f282SAndy Yan #define SRST_I2C1			54
139*bae2f282SAndy Yan #define SRST_I2C2			55
140*bae2f282SAndy Yan #define SRST_I2C3			56
141*bae2f282SAndy Yan #define PRST_PWM1			58
142*bae2f282SAndy Yan #define SRST_PWM1			60
143*bae2f282SAndy Yan #define PRST_WDT			61
144*bae2f282SAndy Yan #define PRST_GPIO1			62
145*bae2f282SAndy Yan #define PRST_GPIO2			63
146*bae2f282SAndy Yan 
147*bae2f282SAndy Yan #define PRST_GPIO3			64
148*bae2f282SAndy Yan #define PRST_GRF			65
149*bae2f282SAndy Yan #define PRST_EFUSE			66
150*bae2f282SAndy Yan #define PRST_EFUSE512			67
151*bae2f282SAndy Yan #define PRST_TIMER0			68
152*bae2f282SAndy Yan #define SRST_TIMER0			69
153*bae2f282SAndy Yan #define SRST_TIMER1			70
154*bae2f282SAndy Yan #define PRST_TSADC			71
155*bae2f282SAndy Yan #define SRST_TSADC			72
156*bae2f282SAndy Yan #define PRST_SARADC			73
157*bae2f282SAndy Yan #define SRST_SARADC			74
158*bae2f282SAndy Yan #define HRST_SYSBUS			75
159*bae2f282SAndy Yan #define PRST_USBGRF			76
160*bae2f282SAndy Yan 
161*bae2f282SAndy Yan #define ARST_PERIPH_NIU		80
162*bae2f282SAndy Yan #define HRST_PERIPH_NIU		81
163*bae2f282SAndy Yan #define PRST_PERIPH_NIU		82
164*bae2f282SAndy Yan #define HRST_PERIPH			83
165*bae2f282SAndy Yan #define HRST_SDMMC			84
166*bae2f282SAndy Yan #define HRST_SDIO			85
167*bae2f282SAndy Yan #define HRST_EMMC			86
168*bae2f282SAndy Yan #define HRST_NANDC			87
169*bae2f282SAndy Yan #define NRST_NANDC			88
170*bae2f282SAndy Yan #define HRST_SFC			89
171*bae2f282SAndy Yan #define SRST_SFC			90
172*bae2f282SAndy Yan #define ARST_GMAC			91
173*bae2f282SAndy Yan #define HRST_OTG			92
174*bae2f282SAndy Yan #define SRST_OTG			93
175*bae2f282SAndy Yan #define SRST_OTG_ADP			94
176*bae2f282SAndy Yan #define HRST_HOST0			95
177*bae2f282SAndy Yan 
178*bae2f282SAndy Yan #define HRST_HOST0_AUX			96
179*bae2f282SAndy Yan #define HRST_HOST0_ARB			97
180*bae2f282SAndy Yan #define SRST_HOST0_EHCIPHY		98
181*bae2f282SAndy Yan #define SRST_HOST0_UTMI		99
182*bae2f282SAndy Yan #define SRST_USBPOR			100
183*bae2f282SAndy Yan #define SRST_UTMI0			101
184*bae2f282SAndy Yan #define SRST_UTMI1			102
185*bae2f282SAndy Yan 
186*bae2f282SAndy Yan #define ARST_VIO0_NIU			102
187*bae2f282SAndy Yan #define ARST_VIO1_NIU			103
188*bae2f282SAndy Yan #define HRST_VIO_NIU			104
189*bae2f282SAndy Yan #define PRST_VIO_NIU			105
190*bae2f282SAndy Yan #define ARST_VOP			106
191*bae2f282SAndy Yan #define HRST_VOP			107
192*bae2f282SAndy Yan #define DRST_VOP			108
193*bae2f282SAndy Yan #define ARST_IEP			109
194*bae2f282SAndy Yan #define HRST_IEP			110
195*bae2f282SAndy Yan #define ARST_RGA			111
196*bae2f282SAndy Yan #define HRST_RGA			112
197*bae2f282SAndy Yan #define SRST_RGA			113
198*bae2f282SAndy Yan #define PRST_CVBS			114
199*bae2f282SAndy Yan #define PRST_HDMI			115
200*bae2f282SAndy Yan #define SRST_HDMI			116
201*bae2f282SAndy Yan #define PRST_MIPI_DSI			117
202*bae2f282SAndy Yan 
203*bae2f282SAndy Yan #define ARST_ISP_NIU			118
204*bae2f282SAndy Yan #define HRST_ISP_NIU			119
205*bae2f282SAndy Yan #define HRST_ISP			120
206*bae2f282SAndy Yan #define SRST_ISP			121
207*bae2f282SAndy Yan #define ARST_VIP0			122
208*bae2f282SAndy Yan #define HRST_VIP0			123
209*bae2f282SAndy Yan #define PRST_VIP0			124
210*bae2f282SAndy Yan #define ARST_VIP1			125
211*bae2f282SAndy Yan #define HRST_VIP1			126
212*bae2f282SAndy Yan #define PRST_VIP1			127
213*bae2f282SAndy Yan #define ARST_VIP2			128
214*bae2f282SAndy Yan #define HRST_VIP2			129
215*bae2f282SAndy Yan #define PRST_VIP2			120
216*bae2f282SAndy Yan #define ARST_VIP3			121
217*bae2f282SAndy Yan #define HRST_VIP3			122
218*bae2f282SAndy Yan #define PRST_VIP4			123
219*bae2f282SAndy Yan 
220*bae2f282SAndy Yan #define PRST_CIF1TO4			124
221*bae2f282SAndy Yan #define SRST_CVBS_CLK			125
222*bae2f282SAndy Yan #define HRST_CVBS			126
223*bae2f282SAndy Yan 
224*bae2f282SAndy Yan #define ARST_VPU_NIU			140
225*bae2f282SAndy Yan #define HRST_VPU_NIU			141
226*bae2f282SAndy Yan #define ARST_VPU			142
227*bae2f282SAndy Yan #define HRST_VPU			143
228*bae2f282SAndy Yan #define ARST_RKVDEC_NIU		144
229*bae2f282SAndy Yan #define HRST_RKVDEC_NIU		145
230*bae2f282SAndy Yan #define ARST_RKVDEC			146
231*bae2f282SAndy Yan #define HRST_RKVDEC			147
232*bae2f282SAndy Yan #define SRST_RKVDEC_CABAC		148
233*bae2f282SAndy Yan #define SRST_RKVDEC_CORE		149
234*bae2f282SAndy Yan #define ARST_RKVENC_NIU		150
235*bae2f282SAndy Yan #define HRST_RKVENC_NIU		151
236*bae2f282SAndy Yan #define ARST_RKVENC			152
237*bae2f282SAndy Yan #define HRST_RKVENC			153
238*bae2f282SAndy Yan #define SRST_RKVENC_CORE		154
239*bae2f282SAndy Yan 
240*bae2f282SAndy Yan #define SRST_DSP_CORE			156
241*bae2f282SAndy Yan #define SRST_DSP_SYS			157
242*bae2f282SAndy Yan #define SRST_DSP_GLOBAL		158
243*bae2f282SAndy Yan #define SRST_DSP_OECM			159
244*bae2f282SAndy Yan #define PRST_DSP_IOP_NIU		160
245*bae2f282SAndy Yan #define ARST_DSP_EPP_NIU		161
246*bae2f282SAndy Yan #define ARST_DSP_EDP_NIU		162
247*bae2f282SAndy Yan #define PRST_DSP_DBG_NIU		163
248*bae2f282SAndy Yan #define PRST_DSP_CFG_NIU		164
249*bae2f282SAndy Yan #define PRST_DSP_GRF			165
250*bae2f282SAndy Yan #define PRST_DSP_MAILBOX		166
251*bae2f282SAndy Yan #define PRST_DSP_INTC			167
252*bae2f282SAndy Yan #define PRST_DSP_PFM_MON		169
253*bae2f282SAndy Yan #define SRST_DSP_PFM_MON		170
254*bae2f282SAndy Yan #define ARST_DSP_EDAP_NIU		171
255*bae2f282SAndy Yan 
256*bae2f282SAndy Yan #define SRST_PMU			172
257*bae2f282SAndy Yan #define SRST_PMU_I2C0			173
258*bae2f282SAndy Yan #define PRST_PMU_I2C0			174
259*bae2f282SAndy Yan #define PRST_PMU_GPIO0			175
260*bae2f282SAndy Yan #define PRST_PMU_INTMEM		176
261*bae2f282SAndy Yan #define PRST_PMU_PWM0			177
262*bae2f282SAndy Yan #define SRST_PMU_PWM0			178
263*bae2f282SAndy Yan #define PRST_PMU_GRF			179
264*bae2f282SAndy Yan #define SRST_PMU_NIU			180
265*bae2f282SAndy Yan #define SRST_PMU_PVTM			181
266*bae2f282SAndy Yan #define ARST_DSP_EDP_PERF		184
267*bae2f282SAndy Yan #define ARST_DSP_EPP_PERF		185
268*bae2f282SAndy Yan 
269*bae2f282SAndy Yan #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
270