1*16b6e4aaSMarek Vasut /* 2*16b6e4aaSMarek Vasut * Copyright (C) 2015 Renesas Electronics Corp. 3*16b6e4aaSMarek Vasut * 4*16b6e4aaSMarek Vasut * This program is free software; you can redistribute it and/or modify 5*16b6e4aaSMarek Vasut * it under the terms of the GNU General Public License as published by 6*16b6e4aaSMarek Vasut * the Free Software Foundation; either version 2 of the License, or 7*16b6e4aaSMarek Vasut * (at your option) any later version. 8*16b6e4aaSMarek Vasut */ 9*16b6e4aaSMarek Vasut 10*16b6e4aaSMarek Vasut #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 11*16b6e4aaSMarek Vasut #define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 12*16b6e4aaSMarek Vasut 13*16b6e4aaSMarek Vasut #include <dt-bindings/clock/renesas-cpg-mssr.h> 14*16b6e4aaSMarek Vasut 15*16b6e4aaSMarek Vasut /* r8a7790 CPG Core Clocks */ 16*16b6e4aaSMarek Vasut #define R8A7790_CLK_Z 0 17*16b6e4aaSMarek Vasut #define R8A7790_CLK_Z2 1 18*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZG 2 19*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZTR 3 20*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZTRD2 4 21*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZT 5 22*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZX 6 23*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZS 7 24*16b6e4aaSMarek Vasut #define R8A7790_CLK_HP 8 25*16b6e4aaSMarek Vasut #define R8A7790_CLK_I 9 26*16b6e4aaSMarek Vasut #define R8A7790_CLK_B 10 27*16b6e4aaSMarek Vasut #define R8A7790_CLK_LB 11 28*16b6e4aaSMarek Vasut #define R8A7790_CLK_P 12 29*16b6e4aaSMarek Vasut #define R8A7790_CLK_CL 13 30*16b6e4aaSMarek Vasut #define R8A7790_CLK_M2 14 31*16b6e4aaSMarek Vasut #define R8A7790_CLK_ADSP 15 32*16b6e4aaSMarek Vasut #define R8A7790_CLK_IMP 16 33*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZB3 17 34*16b6e4aaSMarek Vasut #define R8A7790_CLK_ZB3D2 18 35*16b6e4aaSMarek Vasut #define R8A7790_CLK_DDR 19 36*16b6e4aaSMarek Vasut #define R8A7790_CLK_SDH 20 37*16b6e4aaSMarek Vasut #define R8A7790_CLK_SD0 21 38*16b6e4aaSMarek Vasut #define R8A7790_CLK_SD1 22 39*16b6e4aaSMarek Vasut #define R8A7790_CLK_SD2 23 40*16b6e4aaSMarek Vasut #define R8A7790_CLK_SD3 24 41*16b6e4aaSMarek Vasut #define R8A7790_CLK_MMC0 25 42*16b6e4aaSMarek Vasut #define R8A7790_CLK_MMC1 26 43*16b6e4aaSMarek Vasut #define R8A7790_CLK_MP 27 44*16b6e4aaSMarek Vasut #define R8A7790_CLK_SSP 28 45*16b6e4aaSMarek Vasut #define R8A7790_CLK_SSPRS 29 46*16b6e4aaSMarek Vasut #define R8A7790_CLK_QSPI 30 47*16b6e4aaSMarek Vasut #define R8A7790_CLK_CP 31 48*16b6e4aaSMarek Vasut #define R8A7790_CLK_RCAN 32 49*16b6e4aaSMarek Vasut #define R8A7790_CLK_R 33 50*16b6e4aaSMarek Vasut #define R8A7790_CLK_OSC 34 51*16b6e4aaSMarek Vasut 52*16b6e4aaSMarek Vasut #endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ 53