1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  */
4 
5 /* Core Clocks */
6 #define PLL_HPLL	1
7 #define PLL_DPLL	2
8 #define PLL_D2PLL	3
9 #define PLL_MPLL	4
10 #define ARMCLK		5
11 
12 
13 /* Bus Clocks, derived from core clocks */
14 #define BCLK_PCLK	101
15 #define BCLK_LHCLK	102
16 #define BCLK_MACCLK	103
17 #define BCLK_SDCLK	104
18 #define BCLK_ARMCLK	105
19 #define BCLK_HCLK	106
20 
21 #define MCLK_DDR	201
22 
23 /* Special clocks */
24 #define PCLK_UART1	501
25 #define PCLK_UART2	502
26 #define PCLK_UART3	503
27 #define PCLK_UART4	504
28 #define PCLK_UART5	505
29 #define PCLK_MAC1	506
30 #define PCLK_MAC2	507
31 
32 
33 
34 #define ASPEED_CLK_UART1		46
35 #define ASPEED_CLK_UART2		47
36 #define ASPEED_CLK_UART3		48
37 #define ASPEED_CLK_UART4		49
38 #define ASPEED_CLK_UART5		50
39 
40 
41 
42 
43