xref: /openbmc/u-boot/arch/microblaze/cpu/timer.c (revision bcc05c7a)
1 /*
2  * (C) Copyright 2007 Michal Simek
3  *
4  * Michal  SIMEK <monstr@monstr.eu>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <asm/microblaze_timer.h>
11 #include <asm/microblaze_intc.h>
12 
13 volatile int timestamp = 0;
14 microblaze_timer_t *tmr;
15 
16 ulong get_timer (ulong base)
17 {
18 	if (tmr)
19 		return timestamp - base;
20 	return timestamp++ - base;
21 }
22 
23 void __udelay(unsigned long usec)
24 {
25 	u32 i;
26 
27 	if (tmr) {
28 		i = get_timer(0);
29 		while ((get_timer(0) - i) < (usec / 1000))
30 			;
31 	} else {
32 		for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++)
33 			;
34 	}
35 }
36 
37 static void timer_isr(void *arg)
38 {
39 	timestamp++;
40 	tmr->control = tmr->control | TIMER_INTERRUPT;
41 }
42 
43 int timer_init (void)
44 {
45 	int irq = -1;
46 	u32 preload = 0;
47 	u32 ret = 0;
48 
49 #if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
50 	preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ;
51 	irq = CONFIG_SYS_TIMER_0_IRQ;
52 	tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
53 #endif
54 
55 	if (tmr && preload && irq >= 0) {
56 		tmr->loadreg = preload;
57 		tmr->control = TIMER_INTERRUPT | TIMER_RESET;
58 		tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\
59 					TIMER_RELOAD | TIMER_DOWN_COUNT;
60 		timestamp = 0;
61 		ret = install_interrupt_handler (irq, timer_isr, (void *)tmr);
62 		if (ret)
63 			tmr = NULL;
64 	}
65 
66 	/* No problem if timer is not found/initialized */
67 	return 0;
68 }
69 
70 /*
71  * This function is derived from PowerPC code (read timebase as long long).
72  * On Microblaze it just returns the timer value.
73  */
74 unsigned long long get_ticks(void)
75 {
76 	return get_timer(0);
77 }
78 
79 /*
80  * This function is derived from PowerPC code (timebase clock frequency).
81  * On Microblaze it returns the number of timer ticks per second.
82  */
83 ulong get_tbclk(void)
84 {
85 	return CONFIG_SYS_HZ;
86 }
87