1/* 2 * (C) Copyright 2007 Michal Simek 3 * (C) Copyright 2004 Atmark Techno, Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * Yasushi SHOJI <yashi@atmark-techno.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#include <asm-offsets.h> 12#include <config.h> 13 14 .text 15 .global _start 16_start: 17 /* 18 * reserve registers: 19 * r10: Stores little/big endian offset for vectors 20 * r2: Stores imm opcode 21 * r3: Stores brai opcode 22 */ 23 24 mts rmsr, r0 /* disable cache */ 25 26 addi r8, r0, __end 27 mts rslr, r8 28#if defined(CONFIG_SPL_BUILD) 29 addi r1, r0, CONFIG_SPL_STACK_ADDR 30 mts rshr, r1 31 addi r1, r1, -4 /* Decrement SP to top of memory */ 32#else 33 addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET 34 mts rshr, r1 35 addi r1, r1, -4 /* Decrement SP to top of memory */ 36 37 /* Find-out if u-boot is running on BIG/LITTLE endian platform 38 * There are some steps which is necessary to keep in mind: 39 * 1. Setup offset value to r6 40 * 2. Store word offset value to address 0x0 41 * 3. Load just byte from address 0x0 42 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest 43 * value that's why is on address 0x0 44 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3 45 */ 46 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ 47 lwi r7, r0, 0x28 48 swi r6, r0, 0x28 /* used first unused MB vector */ 49 lbui r10, r0, 0x28 /* used first unused MB vector */ 50 swi r7, r0, 0x28 51 52 /* add opcode instruction for 32bit jump - 2 instruction imm & brai */ 53 addi r2, r0, 0xb0000000 /* hex b000 opcode imm */ 54 addi r3, r0, 0xb8080000 /* hew b808 opcode brai */ 55 56#ifdef CONFIG_SYS_RESET_ADDRESS 57 /* reset address */ 58 swi r2, r0, 0x0 /* reset address - imm opcode */ 59 swi r3, r0, 0x4 /* reset address - brai opcode */ 60 61 addik r6, r0, CONFIG_SYS_RESET_ADDRESS 62 sw r6, r1, r0 63 lhu r7, r1, r10 64 rsubi r8, r10, 0x2 65 sh r7, r0, r8 66 rsubi r8, r10, 0x6 67 sh r6, r0, r8 68#endif 69 70#ifdef CONFIG_SYS_USR_EXCEP 71 /* user_vector_exception */ 72 swi r2, r0, 0x8 /* user vector exception - imm opcode */ 73 swi r3, r0, 0xC /* user vector exception - brai opcode */ 74 75 addik r6, r0, _exception_handler 76 sw r6, r1, r0 77 /* 78 * BIG ENDIAN memory map for user exception 79 * 0x8: 0xB000XXXX 80 * 0xC: 0xB808XXXX 81 * 82 * then it is necessary to count address for storing the most significant 83 * 16bits from _exception_handler address and copy it to 84 * 0xa address. Big endian use offset in r10=0 that's why is it just 85 * 0xa address. The same is done for the least significant 16 bits 86 * for 0xe address. 87 * 88 * LITTLE ENDIAN memory map for user exception 89 * 0x8: 0xXXXX00B0 90 * 0xC: 0xXXXX08B8 91 * 92 * Offset is for little endian setup to 0x2. rsubi instruction decrease 93 * address value to ensure that points to proper place which is 94 * 0x8 for the most significant 16 bits and 95 * 0xC for the least significant 16 bits 96 */ 97 lhu r7, r1, r10 98 rsubi r8, r10, 0xa 99 sh r7, r0, r8 100 rsubi r8, r10, 0xe 101 sh r6, r0, r8 102#endif 103 104 /* interrupt_handler */ 105 swi r2, r0, 0x10 /* interrupt - imm opcode */ 106 swi r3, r0, 0x14 /* interrupt - brai opcode */ 107 108 addik r6, r0, _interrupt_handler 109 sw r6, r1, r0 110 lhu r7, r1, r10 111 rsubi r8, r10, 0x12 112 sh r7, r0, r8 113 rsubi r8, r10, 0x16 114 sh r6, r0, r8 115 116 /* hardware exception */ 117 swi r2, r0, 0x20 /* hardware exception - imm opcode */ 118 swi r3, r0, 0x24 /* hardware exception - brai opcode */ 119 120 addik r6, r0, _hw_exception_handler 121 sw r6, r1, r0 122 lhu r7, r1, r10 123 rsubi r8, r10, 0x22 124 sh r7, r0, r8 125 rsubi r8, r10, 0x26 126 sh r6, r0, r8 127#endif /* BUILD_SPL */ 128 129 /* Flush cache before enable cache */ 130 addik r5, r0, 0 131 addik r6, r0, XILINX_DCACHE_BYTE_SIZE 132flush: bralid r15, flush_cache 133 nop 134 135 /* enable instruction and data cache */ 136 mfs r12, rmsr 137 ori r12, r12, 0x1a0 138 mts rmsr, r12 139 140clear_bss: 141 /* clear BSS segments */ 142 addi r5, r0, __bss_start 143 addi r4, r0, __bss_end 144 cmp r6, r5, r4 145 beqi r6, 3f 1462: 147 swi r0, r5, 0 /* write zero to loc */ 148 addi r5, r5, 4 /* increment to next loc */ 149 cmp r6, r5, r4 /* check if we have reach the end */ 150 bnei r6, 2b 1513: /* jumping to board_init */ 152#ifndef CONFIG_SPL_BUILD 153 brai board_init_f 154#else 155 brai board_init_r 156#endif 1571: bri 1b 158 159#ifndef CONFIG_SPL_BUILD 160/* 161 * Read 16bit little endian 162 */ 163 .text 164 .global in16 165 .ent in16 166 .align 2 167in16: lhu r3, r0, r5 168 bslli r4, r3, 8 169 bsrli r3, r3, 8 170 andi r4, r4, 0xffff 171 or r3, r3, r4 172 rtsd r15, 8 173 sext16 r3, r3 174 .end in16 175 176/* 177 * Write 16bit little endian 178 * first parameter(r5) - address, second(r6) - short value 179 */ 180 .text 181 .global out16 182 .ent out16 183 .align 2 184out16: bslli r3, r6, 8 185 bsrli r6, r6, 8 186 andi r3, r3, 0xffff 187 or r3, r3, r6 188 sh r3, r0, r5 189 rtsd r15, 8 190 or r0, r0, r0 191 .end out16 192#endif 193