1 /* 2 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 28 #include <asm/timer.h> 29 #include <asm/immap.h> 30 #include <watchdog.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 static volatile ulong timestamp = 0; 35 36 #ifndef CONFIG_SYS_WATCHDOG_FREQ 37 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) 38 #endif 39 40 #if defined(CONFIG_MCFTMR) 41 #ifndef CONFIG_SYS_UDELAY_BASE 42 # error "uDelay base not defined!" 43 #endif 44 45 #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK) 46 # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" 47 #endif 48 extern void dtimer_intr_setup(void); 49 50 void __udelay(unsigned long usec) 51 { 52 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE); 53 uint start, now, tmp; 54 55 while (usec > 0) { 56 if (usec > 65000) 57 tmp = 65000; 58 else 59 tmp = usec; 60 usec = usec - tmp; 61 62 /* Set up TIMER 3 as timebase clock */ 63 timerp->tmr = DTIM_DTMR_RST_RST; 64 timerp->tcn = 0; 65 /* set period to 1 us */ 66 timerp->tmr = 67 CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | 68 DTIM_DTMR_RST_EN; 69 70 start = now = timerp->tcn; 71 while (now < start + tmp) 72 now = timerp->tcn; 73 } 74 } 75 76 void dtimer_interrupt(void *not_used) 77 { 78 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE); 79 80 /* check for timer interrupt asserted */ 81 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { 82 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); 83 timestamp++; 84 85 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) 86 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) { 87 WATCHDOG_RESET (); 88 } 89 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ 90 return; 91 } 92 } 93 94 void timer_init(void) 95 { 96 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE); 97 98 timestamp = 0; 99 100 timerp->tcn = 0; 101 timerp->trr = 0; 102 103 /* Set up TIMER 4 as clock */ 104 timerp->tmr = DTIM_DTMR_RST_RST; 105 106 /* initialize and enable timer interrupt */ 107 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); 108 109 timerp->tcn = 0; 110 timerp->trr = 1000; /* Interrupt every ms */ 111 112 dtimer_intr_setup(); 113 114 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ 115 timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | 116 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; 117 } 118 119 ulong get_timer(ulong base) 120 { 121 return (timestamp - base); 122 } 123 124 #endif /* CONFIG_MCFTMR */ 125 126 #if defined(CONFIG_MCFPIT) 127 #if !defined(CONFIG_SYS_PIT_BASE) 128 # error "CONFIG_SYS_PIT_BASE not defined!" 129 #endif 130 131 static unsigned short lastinc; 132 133 void __udelay(unsigned long usec) 134 { 135 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE); 136 uint tmp; 137 138 while (usec > 0) { 139 if (usec > 65000) 140 tmp = 65000; 141 else 142 tmp = usec; 143 usec = usec - tmp; 144 145 /* Set up TIMER 3 as timebase clock */ 146 timerp->pcsr = PIT_PCSR_OVW; 147 timerp->pmr = 0; 148 /* set period to 1 us */ 149 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; 150 151 timerp->pmr = tmp; 152 while (timerp->pcntr > 0) ; 153 } 154 } 155 156 void timer_init(void) 157 { 158 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); 159 timestamp = 0; 160 161 /* Set up TIMER 4 as poll clock */ 162 timerp->pcsr = PIT_PCSR_OVW; 163 timerp->pmr = lastinc = 0; 164 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; 165 } 166 167 ulong get_timer(ulong base) 168 { 169 unsigned short now, diff; 170 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); 171 172 now = timerp->pcntr; 173 diff = -(now - lastinc); 174 175 timestamp += diff; 176 lastinc = now; 177 return timestamp - base; 178 } 179 180 void wait_ticks(unsigned long ticks) 181 { 182 u32 start = get_timer(0); 183 while (get_timer(start) < ticks) ; 184 } 185 #endif /* CONFIG_MCFPIT */ 186 187 /* 188 * This function is derived from PowerPC code (read timebase as long long). 189 * On M68K it just returns the timer value. 190 */ 191 unsigned long long get_ticks(void) 192 { 193 return get_timer(0); 194 } 195 196 unsigned long usec2ticks(unsigned long usec) 197 { 198 return get_timer(usec); 199 } 200 201 /* 202 * This function is derived from PowerPC code (timebase clock frequency). 203 * On M68K it returns the number of timer ticks per second. 204 */ 205 ulong get_tbclk(void) 206 { 207 ulong tbclk; 208 tbclk = CONFIG_SYS_HZ; 209 return tbclk; 210 } 211