xref: /openbmc/u-boot/arch/m68k/lib/cache.c (revision e77e65df)
1 /*
2  * (C) Copyright 2002
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/immap.h>
10 #include <asm/cache.h>
11 
12 volatile int *cf_icache_status = (int *)ICACHE_STATUS;
13 volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
14 
15 void flush_cache(ulong start_addr, ulong size)
16 {
17 	/* Must be implemented for all M68k processors with copy-back data cache */
18 }
19 
20 int icache_status(void)
21 {
22 	return *cf_icache_status;
23 }
24 
25 int dcache_status(void)
26 {
27 	return *cf_dcache_status;
28 }
29 
30 void icache_enable(void)
31 {
32 	icache_invalid();
33 
34 	*cf_icache_status = 1;
35 
36 #ifdef CONFIG_CF_V4
37 	__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
38 	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
39 #elif defined(CONFIG_CF_V4e)
40 	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
41 	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
42 #else
43 	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
44 	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
45 #endif
46 
47 	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
48 }
49 
50 void icache_disable(void)
51 {
52 	u32 temp = 0;
53 
54 	*cf_icache_status = 0;
55 	icache_invalid();
56 
57 #ifdef CONFIG_CF_V4
58 	__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
59 	__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
60 #elif defined(CONFIG_CF_V4e)
61 	__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
62 	__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
63 #else
64 	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
65 	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
66 
67 #endif
68 }
69 
70 void icache_invalid(void)
71 {
72 	u32 temp;
73 
74 	temp = CONFIG_SYS_ICACHE_INV;
75 	if (*cf_icache_status)
76 		temp |= CONFIG_SYS_CACHE_ICACR;
77 
78 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
79 }
80 
81 /*
82  * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
83  * the dcache will be dummy in ColdFire V2 and V3
84  */
85 void dcache_enable(void)
86 {
87 	dcache_invalid();
88 	*cf_dcache_status = 1;
89 
90 #ifdef CONFIG_CF_V4
91 	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
92 	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
93 #elif defined(CONFIG_CF_V4e)
94 	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
95 	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
96 
97 #endif
98 
99 	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
100 }
101 
102 void dcache_disable(void)
103 {
104 	u32 temp = 0;
105 
106 	*cf_dcache_status = 0;
107 	dcache_invalid();
108 
109 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
110 
111 #ifdef CONFIG_CF_V4
112 	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
113 	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
114 #elif defined(CONFIG_CF_V4e)
115 	__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
116 	__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
117 
118 #endif
119 }
120 
121 void dcache_invalid(void)
122 {
123 #ifdef CONFIG_CF_V4
124 	u32 temp;
125 
126 	temp = CONFIG_SYS_DCACHE_INV;
127 	if (*cf_dcache_status)
128 		temp |= CONFIG_SYS_CACHE_DCACR;
129 	if (*cf_icache_status)
130 		temp |= CONFIG_SYS_CACHE_ICACR;
131 
132 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
133 #endif
134 }
135