xref: /openbmc/u-boot/arch/m68k/include/asm/uart.h (revision 1e52fea3)
1 /*
2  * uart.h -- ColdFire internal UART support defines.
3  *
4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 /****************************************************************************/
27 #ifndef	uart_h
28 #define	uart_h
29 /****************************************************************************/
30 
31 /* UART module registers */
32 /* Register read/write struct */
33 typedef struct uart {
34 	u8 umr;			/* 0x00 Mode Register */
35 	u8 resv0[0x3];
36 	union {
37 		u8 usr;		/* 0x04 Status Register */
38 		u8 ucsr;	/* 0x04 Clock Select Register */
39 	};
40 	u8 resv1[0x3];
41 	u8 ucr;			/* 0x08 Command Register */
42 	u8 resv2[0x3];
43 	union {
44 		u8 utb;		/* 0x0c Transmit Buffer */
45 		u8 urb;		/* 0x0c Receive Buffer */
46 	};
47 	u8 resv3[0x3];
48 	union {
49 		u8 uipcr;	/* 0x10 Input Port Change Register */
50 		u8 uacr;	/* 0x10 Auxiliary Control reg */
51 	};
52 	u8 resv4[0x3];
53 	union {
54 		u8 uimr;	/* 0x14 Interrupt Mask reg */
55 		u8 uisr;	/* 0x14 Interrupt Status reg */
56 	};
57 	u8 resv5[0x3];
58 	u8 ubg1;		/* 0x18 Counter Timer Upper Register */
59 	u8 resv6[0x3];
60 	u8 ubg2;		/* 0x1c Counter Timer Lower Register */
61 	u8 resv7[0x17];
62 	u8 uip;			/* 0x34 Input Port Register */
63 	u8 resv8[0x3];
64 	u8 uop1;		/* 0x38 Output Port Set Register */
65 	u8 resv9[0x3];
66 	u8 uop0;		/* 0x3c Output Port Reset Register */
67 } uart_t;
68 
69 /*********************************************************************
70 * Universal Asynchronous Receiver Transmitter (UART)
71 *********************************************************************/
72 /* Bit definitions and macros for UMR */
73 #define UART_UMR_BC(x)			(((x)&0x03))
74 #define UART_UMR_PT			(0x04)
75 #define UART_UMR_PM(x)			(((x)&0x03)<<3)
76 #define UART_UMR_ERR			(0x20)
77 #define UART_UMR_RXIRQ			(0x40)
78 #define UART_UMR_RXRTS			(0x80)
79 #define UART_UMR_SB(x)			(((x)&0x0F))
80 #define UART_UMR_TXCTS			(0x10)	/* Trsnsmit CTS */
81 #define UART_UMR_TXRTS			(0x20)	/* Transmit RTS */
82 #define UART_UMR_CM(x)			(((x)&0x03)<<6)	/* CM bits */
83 #define UART_UMR_PM_MULTI_ADDR		(0x1C)
84 #define UART_UMR_PM_MULTI_DATA		(0x18)
85 #define UART_UMR_PM_NONE		(0x10)
86 #define UART_UMR_PM_FORCE_HI		(0x0C)
87 #define UART_UMR_PM_FORCE_LO		(0x08)
88 #define UART_UMR_PM_ODD			(0x04)
89 #define UART_UMR_PM_EVEN		(0x00)
90 #define UART_UMR_BC_5			(0x00)
91 #define UART_UMR_BC_6			(0x01)
92 #define UART_UMR_BC_7			(0x02)
93 #define UART_UMR_BC_8			(0x03)
94 #define UART_UMR_CM_NORMAL		(0x00)
95 #define UART_UMR_CM_ECH			(0x40)
96 #define UART_UMR_CM_LOCAL_LOOP		(0x80)
97 #define UART_UMR_CM_REMOTE_LOOP		(0xC0)
98 #define UART_UMR_SB_STOP_BITS_1		(0x07)
99 #define UART_UMR_SB_STOP_BITS_15	(0x08)
100 #define UART_UMR_SB_STOP_BITS_2		(0x0F)
101 
102 /* Bit definitions and macros for USR */
103 #define UART_USR_RXRDY			(0x01)
104 #define UART_USR_FFULL			(0x02)
105 #define UART_USR_TXRDY			(0x04)
106 #define UART_USR_TXEMP			(0x08)
107 #define UART_USR_OE			(0x10)
108 #define UART_USR_PE			(0x20)
109 #define UART_USR_FE			(0x40)
110 #define UART_USR_RB			(0x80)
111 
112 /* Bit definitions and macros for UCSR */
113 #define UART_UCSR_TCS(x)		(((x)&0x0F))
114 #define UART_UCSR_RCS(x)		(((x)&0x0F)<<4)
115 #define UART_UCSR_RCS_SYS_CLK		(0xD0)
116 #define UART_UCSR_RCS_CTM16		(0xE0)
117 #define UART_UCSR_RCS_CTM		(0xF0)
118 #define UART_UCSR_TCS_SYS_CLK		(0x0D)
119 #define UART_UCSR_TCS_CTM16		(0x0E)
120 #define UART_UCSR_TCS_CTM		(0x0F)
121 
122 /* Bit definitions and macros for UCR */
123 #define UART_UCR_RXC(x)			(((x)&0x03))
124 #define UART_UCR_TXC(x)			(((x)&0x03)<<2)
125 #define UART_UCR_MISC(x)		(((x)&0x07)<<4)
126 #define UART_UCR_NONE			(0x00)
127 #define UART_UCR_STOP_BREAK		(0x70)
128 #define UART_UCR_START_BREAK		(0x60)
129 #define UART_UCR_BKCHGINT		(0x50)
130 #define UART_UCR_RESET_ERROR		(0x40)
131 #define UART_UCR_RESET_TX		(0x30)
132 #define UART_UCR_RESET_RX		(0x20)
133 #define UART_UCR_RESET_MR		(0x10)
134 #define UART_UCR_TX_DISABLED		(0x08)
135 #define UART_UCR_TX_ENABLED		(0x04)
136 #define UART_UCR_RX_DISABLED		(0x02)
137 #define UART_UCR_RX_ENABLED		(0x01)
138 
139 /* Bit definitions and macros for UIPCR */
140 #define UART_UIPCR_CTS			(0x01)
141 #define UART_UIPCR_COS			(0x10)
142 
143 /* Bit definitions and macros for UACR */
144 #define UART_UACR_IEC			(0x01)
145 
146 /* Bit definitions and macros for UIMR */
147 #define UART_UIMR_TXRDY			(0x01)
148 #define UART_UIMR_RXRDY_FU		(0x02)
149 #define UART_UIMR_DB			(0x04)
150 #define UART_UIMR_COS			(0x80)
151 
152 /* Bit definitions and macros for UISR */
153 #define UART_UISR_TXRDY			(0x01)
154 #define UART_UISR_RXRDY_FU		(0x02)
155 #define UART_UISR_DB			(0x04)
156 #define UART_UISR_RXFTO			(0x08)
157 #define UART_UISR_TXFIFO		(0x10)
158 #define UART_UISR_RXFIFO		(0x20)
159 #define UART_UISR_COS			(0x80)
160 
161 /* Bit definitions and macros for UIP */
162 #define UART_UIP_CTS			(0x01)
163 
164 /* Bit definitions and macros for UOP1 */
165 #define UART_UOP1_RTS			(0x01)
166 
167 /* Bit definitions and macros for UOP0 */
168 #define UART_UOP0_RTS			(0x01)
169 
170 /****************************************************************************/
171 #endif				/* mcfuart_h */
172