1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser /* 3819833afSPeter Tyser * uart.h -- ColdFire internal UART support defines. 4819833afSPeter Tyser * 5819833afSPeter Tyser * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6819833afSPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7819833afSPeter Tyser */ 8819833afSPeter Tyser 9819833afSPeter Tyser /****************************************************************************/ 10819833afSPeter Tyser #ifndef uart_h 11819833afSPeter Tyser #define uart_h 12819833afSPeter Tyser /****************************************************************************/ 13819833afSPeter Tyser 14819833afSPeter Tyser /* UART module registers */ 15819833afSPeter Tyser /* Register read/write struct */ 16819833afSPeter Tyser typedef struct uart { 17819833afSPeter Tyser u8 umr; /* 0x00 Mode Register */ 18819833afSPeter Tyser u8 resv0[0x3]; 19819833afSPeter Tyser union { 20819833afSPeter Tyser u8 usr; /* 0x04 Status Register */ 21819833afSPeter Tyser u8 ucsr; /* 0x04 Clock Select Register */ 22819833afSPeter Tyser }; 23819833afSPeter Tyser u8 resv1[0x3]; 24819833afSPeter Tyser u8 ucr; /* 0x08 Command Register */ 25819833afSPeter Tyser u8 resv2[0x3]; 26819833afSPeter Tyser union { 27819833afSPeter Tyser u8 utb; /* 0x0c Transmit Buffer */ 28819833afSPeter Tyser u8 urb; /* 0x0c Receive Buffer */ 29819833afSPeter Tyser }; 30819833afSPeter Tyser u8 resv3[0x3]; 31819833afSPeter Tyser union { 32819833afSPeter Tyser u8 uipcr; /* 0x10 Input Port Change Register */ 33819833afSPeter Tyser u8 uacr; /* 0x10 Auxiliary Control reg */ 34819833afSPeter Tyser }; 35819833afSPeter Tyser u8 resv4[0x3]; 36819833afSPeter Tyser union { 37819833afSPeter Tyser u8 uimr; /* 0x14 Interrupt Mask reg */ 38819833afSPeter Tyser u8 uisr; /* 0x14 Interrupt Status reg */ 39819833afSPeter Tyser }; 40819833afSPeter Tyser u8 resv5[0x3]; 41819833afSPeter Tyser u8 ubg1; /* 0x18 Counter Timer Upper Register */ 42819833afSPeter Tyser u8 resv6[0x3]; 43819833afSPeter Tyser u8 ubg2; /* 0x1c Counter Timer Lower Register */ 44819833afSPeter Tyser u8 resv7[0x17]; 45819833afSPeter Tyser u8 uip; /* 0x34 Input Port Register */ 46819833afSPeter Tyser u8 resv8[0x3]; 47819833afSPeter Tyser u8 uop1; /* 0x38 Output Port Set Register */ 48819833afSPeter Tyser u8 resv9[0x3]; 49819833afSPeter Tyser u8 uop0; /* 0x3c Output Port Reset Register */ 50819833afSPeter Tyser } uart_t; 51819833afSPeter Tyser 52819833afSPeter Tyser /********************************************************************* 53819833afSPeter Tyser * Universal Asynchronous Receiver Transmitter (UART) 54819833afSPeter Tyser *********************************************************************/ 55819833afSPeter Tyser /* Bit definitions and macros for UMR */ 56819833afSPeter Tyser #define UART_UMR_BC(x) (((x)&0x03)) 57819833afSPeter Tyser #define UART_UMR_PT (0x04) 58819833afSPeter Tyser #define UART_UMR_PM(x) (((x)&0x03)<<3) 59819833afSPeter Tyser #define UART_UMR_ERR (0x20) 60819833afSPeter Tyser #define UART_UMR_RXIRQ (0x40) 61819833afSPeter Tyser #define UART_UMR_RXRTS (0x80) 62819833afSPeter Tyser #define UART_UMR_SB(x) (((x)&0x0F)) 63819833afSPeter Tyser #define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */ 64819833afSPeter Tyser #define UART_UMR_TXRTS (0x20) /* Transmit RTS */ 65819833afSPeter Tyser #define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */ 66819833afSPeter Tyser #define UART_UMR_PM_MULTI_ADDR (0x1C) 67819833afSPeter Tyser #define UART_UMR_PM_MULTI_DATA (0x18) 68819833afSPeter Tyser #define UART_UMR_PM_NONE (0x10) 69819833afSPeter Tyser #define UART_UMR_PM_FORCE_HI (0x0C) 70819833afSPeter Tyser #define UART_UMR_PM_FORCE_LO (0x08) 71819833afSPeter Tyser #define UART_UMR_PM_ODD (0x04) 72819833afSPeter Tyser #define UART_UMR_PM_EVEN (0x00) 73819833afSPeter Tyser #define UART_UMR_BC_5 (0x00) 74819833afSPeter Tyser #define UART_UMR_BC_6 (0x01) 75819833afSPeter Tyser #define UART_UMR_BC_7 (0x02) 76819833afSPeter Tyser #define UART_UMR_BC_8 (0x03) 77819833afSPeter Tyser #define UART_UMR_CM_NORMAL (0x00) 78819833afSPeter Tyser #define UART_UMR_CM_ECH (0x40) 79819833afSPeter Tyser #define UART_UMR_CM_LOCAL_LOOP (0x80) 80819833afSPeter Tyser #define UART_UMR_CM_REMOTE_LOOP (0xC0) 81819833afSPeter Tyser #define UART_UMR_SB_STOP_BITS_1 (0x07) 82819833afSPeter Tyser #define UART_UMR_SB_STOP_BITS_15 (0x08) 83819833afSPeter Tyser #define UART_UMR_SB_STOP_BITS_2 (0x0F) 84819833afSPeter Tyser 85819833afSPeter Tyser /* Bit definitions and macros for USR */ 86819833afSPeter Tyser #define UART_USR_RXRDY (0x01) 87819833afSPeter Tyser #define UART_USR_FFULL (0x02) 88819833afSPeter Tyser #define UART_USR_TXRDY (0x04) 89819833afSPeter Tyser #define UART_USR_TXEMP (0x08) 90819833afSPeter Tyser #define UART_USR_OE (0x10) 91819833afSPeter Tyser #define UART_USR_PE (0x20) 92819833afSPeter Tyser #define UART_USR_FE (0x40) 93819833afSPeter Tyser #define UART_USR_RB (0x80) 94819833afSPeter Tyser 95819833afSPeter Tyser /* Bit definitions and macros for UCSR */ 96819833afSPeter Tyser #define UART_UCSR_TCS(x) (((x)&0x0F)) 97819833afSPeter Tyser #define UART_UCSR_RCS(x) (((x)&0x0F)<<4) 98819833afSPeter Tyser #define UART_UCSR_RCS_SYS_CLK (0xD0) 99819833afSPeter Tyser #define UART_UCSR_RCS_CTM16 (0xE0) 100819833afSPeter Tyser #define UART_UCSR_RCS_CTM (0xF0) 101819833afSPeter Tyser #define UART_UCSR_TCS_SYS_CLK (0x0D) 102819833afSPeter Tyser #define UART_UCSR_TCS_CTM16 (0x0E) 103819833afSPeter Tyser #define UART_UCSR_TCS_CTM (0x0F) 104819833afSPeter Tyser 105819833afSPeter Tyser /* Bit definitions and macros for UCR */ 106819833afSPeter Tyser #define UART_UCR_RXC(x) (((x)&0x03)) 107819833afSPeter Tyser #define UART_UCR_TXC(x) (((x)&0x03)<<2) 108819833afSPeter Tyser #define UART_UCR_MISC(x) (((x)&0x07)<<4) 109819833afSPeter Tyser #define UART_UCR_NONE (0x00) 110819833afSPeter Tyser #define UART_UCR_STOP_BREAK (0x70) 111819833afSPeter Tyser #define UART_UCR_START_BREAK (0x60) 112819833afSPeter Tyser #define UART_UCR_BKCHGINT (0x50) 113819833afSPeter Tyser #define UART_UCR_RESET_ERROR (0x40) 114819833afSPeter Tyser #define UART_UCR_RESET_TX (0x30) 115819833afSPeter Tyser #define UART_UCR_RESET_RX (0x20) 116819833afSPeter Tyser #define UART_UCR_RESET_MR (0x10) 117819833afSPeter Tyser #define UART_UCR_TX_DISABLED (0x08) 118819833afSPeter Tyser #define UART_UCR_TX_ENABLED (0x04) 119819833afSPeter Tyser #define UART_UCR_RX_DISABLED (0x02) 120819833afSPeter Tyser #define UART_UCR_RX_ENABLED (0x01) 121819833afSPeter Tyser 122819833afSPeter Tyser /* Bit definitions and macros for UIPCR */ 123819833afSPeter Tyser #define UART_UIPCR_CTS (0x01) 124819833afSPeter Tyser #define UART_UIPCR_COS (0x10) 125819833afSPeter Tyser 126819833afSPeter Tyser /* Bit definitions and macros for UACR */ 127819833afSPeter Tyser #define UART_UACR_IEC (0x01) 128819833afSPeter Tyser 129819833afSPeter Tyser /* Bit definitions and macros for UIMR */ 130819833afSPeter Tyser #define UART_UIMR_TXRDY (0x01) 131819833afSPeter Tyser #define UART_UIMR_RXRDY_FU (0x02) 132819833afSPeter Tyser #define UART_UIMR_DB (0x04) 133819833afSPeter Tyser #define UART_UIMR_COS (0x80) 134819833afSPeter Tyser 135819833afSPeter Tyser /* Bit definitions and macros for UISR */ 136819833afSPeter Tyser #define UART_UISR_TXRDY (0x01) 137819833afSPeter Tyser #define UART_UISR_RXRDY_FU (0x02) 138819833afSPeter Tyser #define UART_UISR_DB (0x04) 139819833afSPeter Tyser #define UART_UISR_RXFTO (0x08) 140819833afSPeter Tyser #define UART_UISR_TXFIFO (0x10) 141819833afSPeter Tyser #define UART_UISR_RXFIFO (0x20) 142819833afSPeter Tyser #define UART_UISR_COS (0x80) 143819833afSPeter Tyser 144819833afSPeter Tyser /* Bit definitions and macros for UIP */ 145819833afSPeter Tyser #define UART_UIP_CTS (0x01) 146819833afSPeter Tyser 147819833afSPeter Tyser /* Bit definitions and macros for UOP1 */ 148819833afSPeter Tyser #define UART_UOP1_RTS (0x01) 149819833afSPeter Tyser 150819833afSPeter Tyser /* Bit definitions and macros for UOP0 */ 151819833afSPeter Tyser #define UART_UOP0_RTS (0x01) 152819833afSPeter Tyser 153819833afSPeter Tyser /****************************************************************************/ 154819833afSPeter Tyser #endif /* mcfuart_h */ 155