xref: /openbmc/u-boot/arch/m68k/include/asm/timer.h (revision 552a848e)
1 /*
2  * timer.h -- ColdFire internal TIMER support defines.
3  *
4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 /****************************************************************************/
11 #ifndef	timer_h
12 #define	timer_h
13 /****************************************************************************/
14 
15 /****************************************************************************/
16 /* Timer structure */
17 /****************************************************************************/
18 /* DMA Timer module registers */
19 typedef struct dtimer_ctrl {
20 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
21     defined(CONFIG_M5272) || defined(CONFIG_M5307)
22 	u16 tmr;		/* 0x00 Mode register */
23 	u16 res1;		/* 0x02 */
24 	u16 trr;		/* 0x04 Reference register */
25 	u16 res2;		/* 0x06 */
26 	u16 tcr;		/* 0x08 Capture register */
27 	u16 res3;		/* 0x0A */
28 	u16 tcn;		/* 0x0C Counter register */
29 	u16 res4;		/* 0x0E */
30 	u8 res6;		/* 0x10 */
31 	u8 ter;			/* 0x11 Event register */
32 	u16 res7;		/* 0x12 */
33 #else
34 	u16 tmr;		/* 0x00 Mode register */
35 	u8 txmr;		/* 0x02 Extended Mode register */
36 	u8 ter;			/* 0x03 Event register */
37 	u32 trr;		/* 0x04 Reference register */
38 	u32 tcr;		/* 0x08 Capture register */
39 	u32 tcn;		/* 0x0C Counter register */
40 #endif
41 } dtmr_t;
42 
43 /*Programmable Interrupt Timer */
44 typedef struct pit_ctrl {
45 	u16 pcsr;		/* 0x00 Control and Status Register */
46 	u16 pmr;		/* 0x02 Modulus Register */
47 	u16 pcntr;		/* 0x04 Count Register */
48 } pit_t;
49 
50 /*********************************************************************
51 * DMA Timers (DTIM)
52 *********************************************************************/
53 /* Bit definitions and macros for DTMR */
54 #define DTIM_DTMR_RST		(0x0001)	/* Reset */
55 #define DTIM_DTMR_CLK(x)	(((x)&0x0003)<<1)	/* Input clock source */
56 #define DTIM_DTMR_FRR		(0x0008)	/* Free run/restart */
57 #define DTIM_DTMR_ORRI		(0x0010)	/* Output reference request/interrupt enable */
58 #define DTIM_DTMR_OM		(0x0020)	/* Output Mode */
59 #define DTIM_DTMR_CE(x)		(((x)&0x0003)<<6)	/* Capture Edge */
60 #define DTIM_DTMR_PS(x)		(((x)&0x00FF)<<8)	/* Prescaler value */
61 #define DTIM_DTMR_RST_EN	(0x0001)
62 #define DTIM_DTMR_RST_RST	(0x0000)
63 #define DTIM_DTMR_CE_ANY	(0x00C0)
64 #define DTIM_DTMR_CE_FALL	(0x0080)
65 #define DTIM_DTMR_CE_RISE	(0x0040)
66 #define DTIM_DTMR_CE_NONE	(0x0000)
67 #define DTIM_DTMR_CLK_DTIN	(0x0006)
68 #define DTIM_DTMR_CLK_DIV16	(0x0004)
69 #define DTIM_DTMR_CLK_DIV1	(0x0002)
70 #define DTIM_DTMR_CLK_STOP	(0x0000)
71 
72 /* Bit definitions and macros for DTXMR */
73 #define DTIM_DTXMR_MODE16	(0x01)	/* Increment Mode */
74 #define DTIM_DTXMR_DMAEN	(0x80)	/* DMA request */
75 
76 /* Bit definitions and macros for DTER */
77 #define DTIM_DTER_CAP		(0x01)	/* Capture event */
78 #define DTIM_DTER_REF		(0x02)	/* Output reference event */
79 
80 /*********************************************************************
81 *
82 * Programmable Interrupt Timer Modules (PIT)
83 *
84 *********************************************************************/
85 
86 /* Bit definitions and macros for PCSR */
87 #define PIT_PCSR_EN		(0x0001)
88 #define PIT_PCSR_RLD		(0x0002)
89 #define PIT_PCSR_PIF		(0x0004)
90 #define PIT_PCSR_PIE		(0x0008)
91 #define PIT_PCSR_OVW		(0x0010)
92 #define PIT_PCSR_HALTED		(0x0020)
93 #define PIT_PCSR_DOZE		(0x0040)
94 #define PIT_PCSR_PRE(x)		(((x)&0x000F)<<8)
95 
96 /* Bit definitions and macros for PMR */
97 #define PIT_PMR_PM(x)		(x)
98 
99 /* Bit definitions and macros for PCNTR */
100 #define PIT_PCNTR_PC(x)		(x)
101 
102 /****************************************************************************/
103 #endif				/* timer_h */
104