1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * MCF5445x Internal Memory Map 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef __MCF5445X__ 10 #define __MCF5445X__ 11 12 /********************************************************************* 13 * Interrupt Controller (INTC) 14 *********************************************************************/ 15 #define INT0_LO_RSVD0 (0) 16 #define INT0_LO_EPORT1 (1) 17 #define INT0_LO_EPORT2 (2) 18 #define INT0_LO_EPORT3 (3) 19 #define INT0_LO_EPORT4 (4) 20 #define INT0_LO_EPORT5 (5) 21 #define INT0_LO_EPORT6 (6) 22 #define INT0_LO_EPORT7 (7) 23 #define INT0_LO_EDMA_00 (8) 24 #define INT0_LO_EDMA_01 (9) 25 #define INT0_LO_EDMA_02 (10) 26 #define INT0_LO_EDMA_03 (11) 27 #define INT0_LO_EDMA_04 (12) 28 #define INT0_LO_EDMA_05 (13) 29 #define INT0_LO_EDMA_06 (14) 30 #define INT0_LO_EDMA_07 (15) 31 #define INT0_LO_EDMA_08 (16) 32 #define INT0_LO_EDMA_09 (17) 33 #define INT0_LO_EDMA_10 (18) 34 #define INT0_LO_EDMA_11 (19) 35 #define INT0_LO_EDMA_12 (20) 36 #define INT0_LO_EDMA_13 (21) 37 #define INT0_LO_EDMA_14 (22) 38 #define INT0_LO_EDMA_15 (23) 39 #define INT0_LO_EDMA_ERR (24) 40 #define INT0_LO_SCM (25) 41 #define INT0_LO_UART0 (26) 42 #define INT0_LO_UART1 (27) 43 #define INT0_LO_UART2 (28) 44 #define INT0_LO_RSVD1 (29) 45 #define INT0_LO_I2C (30) 46 #define INT0_LO_QSPI (31) 47 #define INT0_HI_DTMR0 (32) 48 #define INT0_HI_DTMR1 (33) 49 #define INT0_HI_DTMR2 (34) 50 #define INT0_HI_DTMR3 (35) 51 #define INT0_HI_FEC0_TXF (36) 52 #define INT0_HI_FEC0_TXB (37) 53 #define INT0_HI_FEC0_UN (38) 54 #define INT0_HI_FEC0_RL (39) 55 #define INT0_HI_FEC0_RXF (40) 56 #define INT0_HI_FEC0_RXB (41) 57 #define INT0_HI_FEC0_MII (42) 58 #define INT0_HI_FEC0_LC (43) 59 #define INT0_HI_FEC0_HBERR (44) 60 #define INT0_HI_FEC0_GRA (45) 61 #define INT0_HI_FEC0_EBERR (46) 62 #define INT0_HI_FEC0_BABT (47) 63 #define INT0_HI_FEC0_BABR (48) 64 #define INT0_HI_FEC1_TXF (49) 65 #define INT0_HI_FEC1_TXB (50) 66 #define INT0_HI_FEC1_UN (51) 67 #define INT0_HI_FEC1_RL (52) 68 #define INT0_HI_FEC1_RXF (53) 69 #define INT0_HI_FEC1_RXB (54) 70 #define INT0_HI_FEC1_MII (55) 71 #define INT0_HI_FEC1_LC (56) 72 #define INT0_HI_FEC1_HBERR (57) 73 #define INT0_HI_FEC1_GRA (58) 74 #define INT0_HI_FEC1_EBERR (59) 75 #define INT0_HI_FEC1_BABT (60) 76 #define INT0_HI_FEC1_BABR (61) 77 #define INT0_HI_SCMIR (62) 78 #define INT0_HI_RTC_ISR (63) 79 80 #define INT1_HI_DSPI_EOQF (33) 81 #define INT1_HI_DSPI_TFFF (34) 82 #define INT1_HI_DSPI_TCF (35) 83 #define INT1_HI_DSPI_TFUF (36) 84 #define INT1_HI_DSPI_RFDF (37) 85 #define INT1_HI_DSPI_RFOF (38) 86 #define INT1_HI_DSPI_RFOF_TFUF (39) 87 #define INT1_HI_RNG_EI (40) 88 #define INT1_HI_PIT0_PIF (43) 89 #define INT1_HI_PIT1_PIF (44) 90 #define INT1_HI_PIT2_PIF (45) 91 #define INT1_HI_PIT3_PIF (46) 92 #define INT1_HI_USBOTG_USBSTS (47) 93 #define INT1_HI_SSI_ISR (49) 94 #define INT1_HI_CCM_UOCSR (53) 95 #define INT1_HI_ATA_ISR (54) 96 #define INT1_HI_PCI_SCR (55) 97 #define INT1_HI_PCI_ASR (56) 98 #define INT1_HI_PLL_LOCKS (57) 99 100 /********************************************************************* 101 * Watchdog Timer Modules (WTM) 102 *********************************************************************/ 103 104 /* Bit definitions and macros for WCR */ 105 #define WTM_WCR_EN (0x0001) 106 #define WTM_WCR_HALTED (0x0002) 107 #define WTM_WCR_DOZE (0x0004) 108 #define WTM_WCR_WAIT (0x0008) 109 110 /********************************************************************* 111 * Serial Boot Facility (SBF) 112 *********************************************************************/ 113 114 /* Bit definitions and macros for SBFCR */ 115 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */ 116 #define SBF_SBFCR_FR (0x0010) /* Fast read */ 117 118 /********************************************************************* 119 * Reset Controller Module (RCM) 120 *********************************************************************/ 121 122 /* Bit definitions and macros for RCR */ 123 #define RCM_RCR_FRCRSTOUT (0x40) 124 #define RCM_RCR_SOFTRST (0x80) 125 126 /* Bit definitions and macros for RSR */ 127 #define RCM_RSR_LOL (0x01) 128 #define RCM_RSR_WDR_CORE (0x02) 129 #define RCM_RSR_EXT (0x04) 130 #define RCM_RSR_POR (0x08) 131 #define RCM_RSR_SOFT (0x20) 132 133 /********************************************************************* 134 * Chip Configuration Module (CCM) 135 *********************************************************************/ 136 137 /* Bit definitions and macros for CCR_360 */ 138 #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */ 139 #define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ 140 #define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ 141 #define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ 142 #define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 143 #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */ 144 #define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ 145 #define CCM_CCR_360_FBCONFIG_MASK (0x00E0) 146 #define CCM_CCR_360_PLLMULT2_MASK (0x0003) 147 #define CCM_CCR_360_PLLMULT3_MASK (0x0007) 148 #define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) 149 #define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) 150 #define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) 151 #define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) 152 #define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) 153 #define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) 154 #define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) 155 #define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) 156 #define CCM_CCR_360_PLLMULT2_12X (0x0000) 157 #define CCM_CCR_360_PLLMULT2_6X (0x0001) 158 #define CCM_CCR_360_PLLMULT2_16X (0x0002) 159 #define CCM_CCR_360_PLLMULT2_8X (0x0003) 160 #define CCM_CCR_360_PLLMULT3_20X (0x0000) 161 #define CCM_CCR_360_PLLMULT3_10X (0x0001) 162 #define CCM_CCR_360_PLLMULT3_24X (0x0002) 163 #define CCM_CCR_360_PLLMULT3_18X (0x0003) 164 #define CCM_CCR_360_PLLMULT3_12X (0x0004) 165 #define CCM_CCR_360_PLLMULT3_6X (0x0005) 166 #define CCM_CCR_360_PLLMULT3_16X (0x0006) 167 #define CCM_CCR_360_PLLMULT3_8X (0x0007) 168 169 /* Bit definitions and macros for CCR_256 */ 170 #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */ 171 #define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ 172 #define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ 173 #define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 174 #define CCM_CCR_256_FBCONFIG_MASK (0x00E0) 175 #define CCM_CCR_256_FBCONFIG_NM_32 (0x0000) 176 #define CCM_CCR_256_FBCONFIG_NM_8 (0x0020) 177 #define CCM_CCR_256_FBCONFIG_NM_16 (0x0040) 178 #define CCM_CCR_256_FBCONFIG_M_32 (0x0080) 179 #define CCM_CCR_256_FBCONFIG_M_8 (0x00A0) 180 #define CCM_CCR_256_FBCONFIG_M_16 (0x00C0) 181 #define CCM_CCR_256_PLLMULT3_MASK (0x0007) 182 #define CCM_CCR_256_PLLMULT3_20X (0x0000) 183 #define CCM_CCR_256_PLLMULT3_10X (0x0001) 184 #define CCM_CCR_256_PLLMULT3_24X (0x0002) 185 #define CCM_CCR_256_PLLMULT3_18X (0x0003) 186 #define CCM_CCR_256_PLLMULT3_12X (0x0004) 187 #define CCM_CCR_256_PLLMULT3_6X (0x0005) 188 #define CCM_CCR_256_PLLMULT3_16X (0x0006) 189 #define CCM_CCR_256_PLLMULT3_8X (0x0007) 190 191 /* Bit definitions and macros for RCON_360 */ 192 #define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ 193 #define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ 194 #define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ 195 #define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ 196 #define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 197 198 /* Bit definitions and macros for RCON_256 */ 199 #define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */ 200 #define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ 201 #define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ 202 #define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */ 203 204 /* Bit definitions and macros for CIR */ 205 #define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ 206 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ 207 #define CCM_CIR_PIN_MASK (0xFFC0) 208 #define CCM_CIR_PRN_MASK (0x003F) 209 #define CCM_CIR_PIN_MCF54450 (0x4F<<6) 210 #define CCM_CIR_PIN_MCF54451 (0x4D<<6) 211 #define CCM_CIR_PIN_MCF54452 (0x4B<<6) 212 #define CCM_CIR_PIN_MCF54453 (0x49<<6) 213 #define CCM_CIR_PIN_MCF54454 (0x4A<<6) 214 #define CCM_CIR_PIN_MCF54455 (0x48<<6) 215 216 /* Bit definitions and macros for MISCCR */ 217 #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ 218 #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ 219 #define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ 220 #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ 221 #define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ 222 #define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ 223 #define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ 224 #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */ 225 #define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ 226 #define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ 227 #define CCM_MISCCR_BMT_65536 (0) 228 #define CCM_MISCCR_BMT_32768 (1) 229 #define CCM_MISCCR_BMT_16384 (2) 230 #define CCM_MISCCR_BMT_8192 (3) 231 #define CCM_MISCCR_BMT_4096 (4) 232 #define CCM_MISCCR_BMT_2048 (5) 233 #define CCM_MISCCR_BMT_1024 (6) 234 #define CCM_MISCCR_BMT_512 (7) 235 #define CCM_MISCCR_SSIPUS_UP (1) 236 #define CCM_MISCCR_SSIPUS_DOWN (0) 237 #define CCM_MISCCR_TIMDMA_TIM (1) 238 #define CCM_MISCCR_TIMDMA_SSI (0) 239 #define CCM_MISCCR_SSISRC_CLKIN (0) 240 #define CCM_MISCCR_SSISRC_PLL (1) 241 #define CCM_MISCCR_USBOC_ACTHI (0) 242 #define CCM_MISCCR_USBOV_ACTLO (1) 243 #define CCM_MISCCR_USBSRC_CLKIN (0) 244 #define CCM_MISCCR_USBSRC_PLL (1) 245 246 /* Bit definitions and macros for CDR */ 247 #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */ 248 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */ 249 250 /* Bit definitions and macros for UOCSR */ 251 #define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ 252 #define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ 253 #define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ 254 #define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ 255 #define CCM_UOCSR_SEND (0x0010) /* Session end */ 256 #define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ 257 #define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ 258 #define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ 259 #define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ 260 #define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ 261 #define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ 262 #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ 263 #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ 264 265 /********************************************************************* 266 * General Purpose I/O Module (GPIO) 267 *********************************************************************/ 268 269 /* Bit definitions and macros for PAR_FEC */ 270 #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) 271 #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) 272 #define GPIO_PAR_FEC_FEC1_UNMASK (0x8F) 273 #define GPIO_PAR_FEC_FEC1_MII (0x70) 274 #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) 275 #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) 276 #define GPIO_PAR_FEC_FEC1_ATA (0x10) 277 #define GPIO_PAR_FEC_FEC1_GPIO (0x00) 278 #define GPIO_PAR_FEC_FEC0_UNMASK (0xF8) 279 #define GPIO_PAR_FEC_FEC0_MII (0x07) 280 #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) 281 #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) 282 #define GPIO_PAR_FEC_FEC0_ULPI (0x01) 283 #define GPIO_PAR_FEC_FEC0_GPIO (0x00) 284 285 /* Bit definitions and macros for PAR_DMA */ 286 #define GPIO_PAR_DMA_DREQ0 (0x01) 287 #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) 288 #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) 289 #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) 290 #define GPIO_PAR_DMA_DACK1_UNMASK (0x3F) 291 #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0) 292 #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) 293 #define GPIO_PAR_DMA_DACK1_GPIO (0x00) 294 #define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF) 295 #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) 296 #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) 297 #define GPIO_PAR_DMA_DREQ1_GPIO (0x00) 298 #define GPIO_PAR_DMA_DACK0_UNMASK (0xF3) 299 #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C) 300 #define GPIO_PAR_DMA_DACK0_PCS3 (0x08) 301 #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) 302 #define GPIO_PAR_DMA_DACK0_GPIO (0x00) 303 #define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) 304 #define GPIO_PAR_DMA_DREQ0_GPIO (0x00) 305 306 /* Bit definitions and macros for PAR_FBCTL */ 307 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) 308 #define GPIO_PAR_FBCTL_RW (0x20) 309 #define GPIO_PAR_FBCTL_TA (0x40) 310 #define GPIO_PAR_FBCTL_OE (0x80) 311 #define GPIO_PAR_FBCTL_OE_OE (0x80) 312 #define GPIO_PAR_FBCTL_OE_GPIO (0x00) 313 #define GPIO_PAR_FBCTL_TA_TA (0x40) 314 #define GPIO_PAR_FBCTL_TA_GPIO (0x00) 315 #define GPIO_PAR_FBCTL_RW_RW (0x20) 316 #define GPIO_PAR_FBCTL_RW_GPIO (0x00) 317 #define GPIO_PAR_FBCTL_TS_UNMASK (0xE7) 318 #define GPIO_PAR_FBCTL_TS_TS (0x18) 319 #define GPIO_PAR_FBCTL_TS_ALE (0x10) 320 #define GPIO_PAR_FBCTL_TS_TBST (0x08) 321 #define GPIO_PAR_FBCTL_TS_GPIO (0x80) 322 323 /* Bit definitions and macros for PAR_DSPI */ 324 #define GPIO_PAR_DSPI_SCK (0x01) 325 #define GPIO_PAR_DSPI_SOUT (0x02) 326 #define GPIO_PAR_DSPI_SIN (0x04) 327 #define GPIO_PAR_DSPI_PCS0 (0x08) 328 #define GPIO_PAR_DSPI_PCS1 (0x10) 329 #define GPIO_PAR_DSPI_PCS2 (0x20) 330 #define GPIO_PAR_DSPI_PCS5 (0x40) 331 #define GPIO_PAR_DSPI_PCS5_PCS5 (0x40) 332 #define GPIO_PAR_DSPI_PCS5_GPIO (0x00) 333 #define GPIO_PAR_DSPI_PCS2_PCS2 (0x20) 334 #define GPIO_PAR_DSPI_PCS2_GPIO (0x00) 335 #define GPIO_PAR_DSPI_PCS1_PCS1 (0x10) 336 #define GPIO_PAR_DSPI_PCS1_GPIO (0x00) 337 #define GPIO_PAR_DSPI_PCS0_PCS0 (0x08) 338 #define GPIO_PAR_DSPI_PCS0_GPIO (0x00) 339 #define GPIO_PAR_DSPI_SIN_SIN (0x04) 340 #define GPIO_PAR_DSPI_SIN_GPIO (0x00) 341 #define GPIO_PAR_DSPI_SOUT_SOUT (0x02) 342 #define GPIO_PAR_DSPI_SOUT_GPIO (0x00) 343 #define GPIO_PAR_DSPI_SCK_SCK (0x01) 344 #define GPIO_PAR_DSPI_SCK_GPIO (0x00) 345 346 /* Bit definitions and macros for PAR_BE */ 347 #define GPIO_PAR_BE_BS0 (0x01) 348 #define GPIO_PAR_BE_BS1 (0x04) 349 #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) 350 #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) 351 #define GPIO_PAR_BE_BE3_UNMASK (0x3F) 352 #define GPIO_PAR_BE_BE3_BE3 (0xC0) 353 #define GPIO_PAR_BE_BE3_TSIZ1 (0x80) 354 #define GPIO_PAR_BE_BE3_GPIO (0x00) 355 #define GPIO_PAR_BE_BE2_UNMASK (0xCF) 356 #define GPIO_PAR_BE_BE2_BE2 (0x30) 357 #define GPIO_PAR_BE_BE2_TSIZ0 (0x20) 358 #define GPIO_PAR_BE_BE2_GPIO (0x00) 359 #define GPIO_PAR_BE_BE1_BE1 (0x04) 360 #define GPIO_PAR_BE_BE1_GPIO (0x00) 361 #define GPIO_PAR_BE_BE0_BE0 (0x01) 362 #define GPIO_PAR_BE_BE0_GPIO (0x00) 363 364 /* Bit definitions and macros for PAR_CS */ 365 #define GPIO_PAR_CS_CS1 (0x02) 366 #define GPIO_PAR_CS_CS2 (0x04) 367 #define GPIO_PAR_CS_CS3 (0x08) 368 #define GPIO_PAR_CS_CS3_CS3 (0x08) 369 #define GPIO_PAR_CS_CS3_GPIO (0x00) 370 #define GPIO_PAR_CS_CS2_CS2 (0x04) 371 #define GPIO_PAR_CS_CS2_GPIO (0x00) 372 #define GPIO_PAR_CS_CS1_CS1 (0x02) 373 #define GPIO_PAR_CS_CS1_GPIO (0x00) 374 375 /* Bit definitions and macros for PAR_TIMER */ 376 #define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) 377 #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) 378 #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) 379 #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) 380 #define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F) 381 #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) 382 #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) 383 #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40) 384 #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) 385 #define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF) 386 #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) 387 #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) 388 #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10) 389 #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) 390 #define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3) 391 #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) 392 #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) 393 #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04) 394 #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) 395 #define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC) 396 #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) 397 #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) 398 #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01) 399 #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) 400 401 /* Bit definitions and macros for PAR_USB */ 402 #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) 403 #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) 404 #define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3) 405 #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) 406 #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) 407 #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) 408 #define GPIO_PAR_USB_VBUSEN_GPIO (0x00) 409 #define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC) 410 #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) 411 #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) 412 #define GPIO_PAR_USB_VBUSOC_GPIO (0x00) 413 414 /* Bit definitions and macros for PAR_UART */ 415 #define GPIO_PAR_UART_U0TXD (0x01) 416 #define GPIO_PAR_UART_U0RXD (0x02) 417 #define GPIO_PAR_UART_U0RTS (0x04) 418 #define GPIO_PAR_UART_U0CTS (0x08) 419 #define GPIO_PAR_UART_U1TXD (0x10) 420 #define GPIO_PAR_UART_U1RXD (0x20) 421 #define GPIO_PAR_UART_U1RTS (0x40) 422 #define GPIO_PAR_UART_U1CTS (0x80) 423 #define GPIO_PAR_UART_U1CTS_U1CTS (0x80) 424 #define GPIO_PAR_UART_U1CTS_GPIO (0x00) 425 #define GPIO_PAR_UART_U1RTS_U1RTS (0x40) 426 #define GPIO_PAR_UART_U1RTS_GPIO (0x00) 427 #define GPIO_PAR_UART_U1RXD_U1RXD (0x20) 428 #define GPIO_PAR_UART_U1RXD_GPIO (0x00) 429 #define GPIO_PAR_UART_U1TXD_U1TXD (0x10) 430 #define GPIO_PAR_UART_U1TXD_GPIO (0x00) 431 #define GPIO_PAR_UART_U0CTS_U0CTS (0x08) 432 #define GPIO_PAR_UART_U0CTS_GPIO (0x00) 433 #define GPIO_PAR_UART_U0RTS_U0RTS (0x04) 434 #define GPIO_PAR_UART_U0RTS_GPIO (0x00) 435 #define GPIO_PAR_UART_U0RXD_U0RXD (0x02) 436 #define GPIO_PAR_UART_U0RXD_GPIO (0x00) 437 #define GPIO_PAR_UART_U0TXD_U0TXD (0x01) 438 #define GPIO_PAR_UART_U0TXD_GPIO (0x00) 439 440 /* Bit definitions and macros for PAR_FECI2C */ 441 #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) 442 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) 443 #define GPIO_PAR_FECI2C_MDIO0 (0x0010) 444 #define GPIO_PAR_FECI2C_MDC0 (0x0040) 445 #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) 446 #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) 447 #define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF) 448 #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) 449 #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) 450 #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) 451 #define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF) 452 #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) 453 #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) 454 #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) 455 #define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) 456 #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) 457 #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) 458 #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) 459 #define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3) 460 #define GPIO_PAR_FECI2C_SCL_SCL (0x000C) 461 #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) 462 #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000) 463 #define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC) 464 #define GPIO_PAR_FECI2C_SDA_SDA (0x0003) 465 #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) 466 #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000) 467 468 /* Bit definitions and macros for PAR_SSI */ 469 #define GPIO_PAR_SSI_MCLK (0x0001) 470 #define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) 471 #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) 472 #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) 473 #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) 474 #define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF) 475 #define GPIO_PAR_SSI_BCLK_BCLK (0x0300) 476 #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200) 477 #define GPIO_PAR_SSI_BCLK_GPIO (0x0000) 478 #define GPIO_PAR_SSI_FS_UNMASK (0xFF3F) 479 #define GPIO_PAR_SSI_FS_FS (0x00C0) 480 #define GPIO_PAR_SSI_FS_U1RTS (0x0080) 481 #define GPIO_PAR_SSI_FS_GPIO (0x0000) 482 #define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF) 483 #define GPIO_PAR_SSI_SRXD_SRXD (0x0030) 484 #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020) 485 #define GPIO_PAR_SSI_SRXD_GPIO (0x0000) 486 #define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3) 487 #define GPIO_PAR_SSI_STXD_STXD (0x000C) 488 #define GPIO_PAR_SSI_STXD_U1TXD (0x0008) 489 #define GPIO_PAR_SSI_STXD_GPIO (0x0000) 490 #define GPIO_PAR_SSI_MCLK_MCLK (0x0001) 491 #define GPIO_PAR_SSI_MCLK_GPIO (0x0000) 492 493 /* Bit definitions and macros for PAR_ATA */ 494 #define GPIO_PAR_ATA_IORDY (0x0001) 495 #define GPIO_PAR_ATA_DMARQ (0x0002) 496 #define GPIO_PAR_ATA_RESET (0x0004) 497 #define GPIO_PAR_ATA_DA0 (0x0020) 498 #define GPIO_PAR_ATA_DA1 (0x0040) 499 #define GPIO_PAR_ATA_DA2 (0x0080) 500 #define GPIO_PAR_ATA_CS0 (0x0100) 501 #define GPIO_PAR_ATA_CS1 (0x0200) 502 #define GPIO_PAR_ATA_BUFEN (0x0400) 503 #define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) 504 #define GPIO_PAR_ATA_BUFEN_GPIO (0x0000) 505 #define GPIO_PAR_ATA_CS1_CS1 (0x0200) 506 #define GPIO_PAR_ATA_CS1_GPIO (0x0000) 507 #define GPIO_PAR_ATA_CS0_CS0 (0x0100) 508 #define GPIO_PAR_ATA_CS0_GPIO (0x0000) 509 #define GPIO_PAR_ATA_DA2_DA2 (0x0080) 510 #define GPIO_PAR_ATA_DA2_GPIO (0x0000) 511 #define GPIO_PAR_ATA_DA1_DA1 (0x0040) 512 #define GPIO_PAR_ATA_DA1_GPIO (0x0000) 513 #define GPIO_PAR_ATA_DA0_DA0 (0x0020) 514 #define GPIO_PAR_ATA_DA0_GPIO (0x0000) 515 #define GPIO_PAR_ATA_RESET_RESET (0x0004) 516 #define GPIO_PAR_ATA_RESET_GPIO (0x0000) 517 #define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) 518 #define GPIO_PAR_ATA_DMARQ_GPIO (0x0000) 519 #define GPIO_PAR_ATA_IORDY_IORDY (0x0001) 520 #define GPIO_PAR_ATA_IORDY_GPIO (0x0000) 521 522 /* Bit definitions and macros for PAR_IRQ */ 523 #define GPIO_PAR_IRQ_IRQ1 (0x02) 524 #define GPIO_PAR_IRQ_IRQ4 (0x10) 525 #define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) 526 #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) 527 #define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) 528 #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) 529 530 /* Bit definitions and macros for PAR_PCI */ 531 #define GPIO_PAR_PCI_REQ0 (0x0001) 532 #define GPIO_PAR_PCI_REQ1 (0x0004) 533 #define GPIO_PAR_PCI_REQ2 (0x0010) 534 #define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) 535 #define GPIO_PAR_PCI_GNT0 (0x0100) 536 #define GPIO_PAR_PCI_GNT1 (0x0400) 537 #define GPIO_PAR_PCI_GNT2 (0x1000) 538 #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) 539 #define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF) 540 #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000) 541 #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) 542 #define GPIO_PAR_PCI_GNT3_GPIO (0x0000) 543 #define GPIO_PAR_PCI_GNT2_GNT2 (0x1000) 544 #define GPIO_PAR_PCI_GNT2_GPIO (0x0000) 545 #define GPIO_PAR_PCI_GNT1_GNT1 (0x0400) 546 #define GPIO_PAR_PCI_GNT1_GPIO (0x0000) 547 #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100) 548 #define GPIO_PAR_PCI_GNT0_GPIO (0x0000) 549 #define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F) 550 #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) 551 #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) 552 #define GPIO_PAR_PCI_REQ3_GPIO (0x0000) 553 #define GPIO_PAR_PCI_REQ2_REQ2 (0x0010) 554 #define GPIO_PAR_PCI_REQ2_GPIO (0x0000) 555 #define GPIO_PAR_PCI_REQ1_REQ1 (0x0040) 556 #define GPIO_PAR_PCI_REQ1_GPIO (0x0000) 557 #define GPIO_PAR_PCI_REQ0_REQ0 (0x0001) 558 #define GPIO_PAR_PCI_REQ0_GPIO (0x0000) 559 560 /* Bit definitions and macros for MSCR_SDRAM */ 561 #define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) 562 #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) 563 #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) 564 #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) 565 #define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F) 566 #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) 567 #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) 568 #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) 569 #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) 570 #define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF) 571 #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) 572 #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) 573 #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) 574 #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) 575 #define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3) 576 #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) 577 #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) 578 #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) 579 #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) 580 #define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC) 581 #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) 582 #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) 583 #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) 584 #define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) 585 586 /* Bit definitions and macros for MSCR_PCI */ 587 #define GPIO_MSCR_PCI_PCI (0x01) 588 #define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) 589 #define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) 590 591 /* Bit definitions and macros for DSCR_I2C */ 592 #define GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) 593 #define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) 594 #define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) 595 #define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) 596 #define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) 597 598 /* Bit definitions and macros for DSCR_FLEXBUS */ 599 #define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) 600 #define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) 601 #define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) 602 #define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) 603 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) 604 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80) 605 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) 606 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) 607 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) 608 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) 609 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) 610 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) 611 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) 612 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) 613 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) 614 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) 615 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) 616 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) 617 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) 618 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) 619 620 /* Bit definitions and macros for DSCR_FEC */ 621 #define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) 622 #define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) 623 #define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) 624 #define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) 625 #define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) 626 #define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) 627 #define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) 628 #define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) 629 #define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) 630 #define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) 631 632 /* Bit definitions and macros for DSCR_UART */ 633 #define GPIO_DSCR_UART_UART0(x) (((x)&0x03)) 634 #define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) 635 #define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) 636 #define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) 637 #define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) 638 #define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) 639 #define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) 640 #define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) 641 #define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) 642 #define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) 643 644 /* Bit definitions and macros for DSCR_DSPI */ 645 #define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) 646 #define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) 647 #define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) 648 #define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) 649 #define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) 650 651 /* Bit definitions and macros for DSCR_TIMER */ 652 #define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) 653 #define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) 654 #define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) 655 #define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) 656 #define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) 657 658 /* Bit definitions and macros for DSCR_SSI */ 659 #define GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) 660 #define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) 661 #define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) 662 #define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) 663 #define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) 664 665 /* Bit definitions and macros for DSCR_DMA */ 666 #define GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) 667 #define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) 668 #define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) 669 #define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) 670 #define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) 671 672 /* Bit definitions and macros for DSCR_DEBUG */ 673 #define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) 674 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) 675 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) 676 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) 677 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) 678 679 /* Bit definitions and macros for DSCR_RESET */ 680 #define GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) 681 #define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) 682 #define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) 683 #define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) 684 #define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) 685 686 /* Bit definitions and macros for DSCR_IRQ */ 687 #define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) 688 #define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) 689 #define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) 690 #define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) 691 #define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) 692 693 /* Bit definitions and macros for DSCR_USB */ 694 #define GPIO_DSCR_USB_USB(x) (((x)&0x03)) 695 #define GPIO_DSCR_USB_USB_LOAD_50PF (0x03) 696 #define GPIO_DSCR_USB_USB_LOAD_30PF (0x02) 697 #define GPIO_DSCR_USB_USB_LOAD_20PF (0x01) 698 #define GPIO_DSCR_USB_USB_LOAD_10PF (0x00) 699 700 /* Bit definitions and macros for DSCR_ATA */ 701 #define GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) 702 #define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) 703 #define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) 704 #define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) 705 #define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) 706 707 /********************************************************************* 708 * SDRAM Controller (SDRAMC) 709 *********************************************************************/ 710 711 /* Bit definitions and macros for SDMR */ 712 #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ 713 #define SDRAMC_SDMR_CMD (0x00010000) /* Command */ 714 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ 715 #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ 716 #define SDRAMC_SDMR_BK_LMR (0x00000000) 717 #define SDRAMC_SDMR_BK_LEMR (0x40000000) 718 719 /* Bit definitions and macros for SDCR */ 720 #define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ 721 #define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ 722 #define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ 723 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ 724 #define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ 725 #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ 726 #define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ 727 #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ 728 #define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ 729 #define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ 730 #define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ 731 #define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ 732 #define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ 733 #define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) 734 735 /* Bit definitions and macros for SDCFG1 */ 736 #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ 737 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ 738 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ 739 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ 740 #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ 741 #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ 742 #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ 743 744 /* Bit definitions and macros for SDCFG2 */ 745 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ 746 #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ 747 #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ 748 #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ 749 750 /* Bit definitions and macros for SDCS group */ 751 #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ 752 #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ 753 #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) 754 #define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) 755 #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) 756 #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) 757 #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) 758 #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) 759 #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) 760 #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) 761 #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) 762 #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) 763 #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) 764 #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) 765 #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) 766 #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 767 #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 768 769 /********************************************************************* 770 * Phase Locked Loop (PLL) 771 *********************************************************************/ 772 773 /* Bit definitions and macros for PCR */ 774 #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ 775 #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */ 776 #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */ 777 #define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */ 778 #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ 779 #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ 780 #define PLL_PCR_PFDR_MASK (0x000F0000) 781 #define PLL_PCR_OUTDIV5_MASK (0x000F0000) 782 #define PLL_PCR_OUTDIV4_MASK (0x0000F000) 783 #define PLL_PCR_OUTDIV3_MASK (0x00000F00) 784 #define PLL_PCR_OUTDIV2_MASK (0x000000F0) 785 #define PLL_PCR_OUTDIV1_MASK (0x0000000F) 786 787 /* Bit definitions and macros for PSR */ 788 #define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ 789 #define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ 790 #define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ 791 #define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ 792 793 /********************************************************************* 794 * PCI 795 *********************************************************************/ 796 797 /* Bit definitions and macros for SCR */ 798 #define PCI_SCR_PE (0x80000000) /* Parity Error detected */ 799 #define PCI_SCR_SE (0x40000000) /* System error signalled */ 800 #define PCI_SCR_MA (0x20000000) /* Master aboart received */ 801 #define PCI_SCR_TR (0x10000000) /* Target abort received */ 802 #define PCI_SCR_TS (0x08000000) /* Target abort signalled */ 803 #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ 804 #define PCI_SCR_DP (0x01000000) /* Master data parity err */ 805 #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ 806 #define PCI_SCR_R (0x00400000) /* Reserved */ 807 #define PCI_SCR_66M (0x00200000) /* 66Mhz */ 808 #define PCI_SCR_C (0x00100000) /* Capabilities list */ 809 #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ 810 #define PCI_SCR_S (0x00000100) /* SERR enable */ 811 #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ 812 #define PCI_SCR_PER (0x00000040) /* Parity error response */ 813 #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ 814 #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ 815 #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ 816 #define PCI_SCR_B (0x00000004) /* Bus master enable */ 817 #define PCI_SCR_M (0x00000002) /* Memory access control */ 818 #define PCI_SCR_IO (0x00000001) /* I/O access control */ 819 820 #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ 821 #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ 822 #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ 823 #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ 824 825 #define PCI_BAR_BAR0(x) (x & 0xFFFC0000) 826 #define PCI_BAR_BAR1(x) (x & 0xFFF00000) 827 #define PCI_BAR_BAR2(x) (x & 0xFFC00000) 828 #define PCI_BAR_BAR3(x) (x & 0xFF000000) 829 #define PCI_BAR_BAR4(x) (x & 0xF8000000) 830 #define PCI_BAR_BAR5(x) (x & 0xE0000000) 831 #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ 832 #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ 833 #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ 834 835 #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ 836 #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ 837 #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ 838 #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ 839 840 #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ 841 #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ 842 #define PCI_GSCR_SE (0x10000000) /* SERR detected */ 843 #define PCI_GSCR_ER (0x08000000) /* Error response detected */ 844 #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ 845 #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ 846 #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ 847 #define PCI_GSCR_PR (0x00000001) /* PCI reset */ 848 849 #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ 850 #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ 851 #define PCI_TCR1_P (0x00010000) /* Prefetch reads */ 852 #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ 853 854 #define PCI_TCR2_B5E (0x00002000) /* */ 855 #define PCI_TCR2_B4E (0x00001000) /* */ 856 #define PCI_TCR2_B3E (0x00000800) /* */ 857 #define PCI_TCR2_B2E (0x00000400) /* */ 858 #define PCI_TCR2_B1E (0x00000200) /* */ 859 #define PCI_TCR2_B0E (0x00000100) /* */ 860 #define PCI_TCR2_CR (0x00000001) /* */ 861 862 #define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) 863 #define PCI_TBATR_EN (0x00000001) /* Enable */ 864 865 #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ 866 #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ 867 #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ 868 #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ 869 #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ 870 #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ 871 #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ 872 #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ 873 #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ 874 #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ 875 #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ 876 #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ 877 #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ 878 #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ 879 #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ 880 881 #define PCI_ICR_REE (0x04000000) /* Retry error enable */ 882 #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ 883 #define PCI_ICR_TAE (0x01000000) /* Target abort enable */ 884 #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) 885 886 /********************************************************************/ 887 888 #endif /* __MCF5445X__ */ 889