1 /* 2 * MCF5441X Internal Memory Map 3 * 4 * Copyright 2010-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __MCF5441X__ 27 #define __MCF5441X__ 28 29 /* Interrupt Controller (INTC) */ 30 #define INT0_LO_RSVD0 (0) 31 #define INT0_LO_EPORT1 (1) 32 #define INT0_LO_EPORT2 (2) 33 #define INT0_LO_EPORT3 (3) 34 #define INT0_LO_EPORT4 (4) 35 #define INT0_LO_EPORT5 (5) 36 #define INT0_LO_EPORT6 (6) 37 #define INT0_LO_EPORT7 (7) 38 #define INT0_LO_EDMA_00 (8) 39 #define INT0_LO_EDMA_01 (9) 40 #define INT0_LO_EDMA_02 (10) 41 #define INT0_LO_EDMA_03 (11) 42 #define INT0_LO_EDMA_04 (12) 43 #define INT0_LO_EDMA_05 (13) 44 #define INT0_LO_EDMA_06 (14) 45 #define INT0_LO_EDMA_07 (15) 46 #define INT0_LO_EDMA_08 (16) 47 #define INT0_LO_EDMA_09 (17) 48 #define INT0_LO_EDMA_10 (18) 49 #define INT0_LO_EDMA_11 (19) 50 #define INT0_LO_EDMA_12 (20) 51 #define INT0_LO_EDMA_13 (21) 52 #define INT0_LO_EDMA_14 (22) 53 #define INT0_LO_EDMA_15 (23) 54 #define INT0_LO_EDMA_ERR (24) 55 #define INT0_LO_SCM (25) 56 #define INT0_LO_UART0 (26) 57 #define INT0_LO_UART1 (27) 58 #define INT0_LO_UART2 (28) 59 #define INT0_LO_UART3 (29) 60 #define INT0_LO_I2C0 (30) 61 #define INT0_LO_DSPI0 (31) 62 #define INT0_HI_DTMR0 (32) 63 #define INT0_HI_DTMR1 (33) 64 #define INT0_HI_DTMR2 (34) 65 #define INT0_HI_DTMR3 (35) 66 #define INT0_HI_MACNET0_TXF (36) 67 #define INT0_HI_MACNET0_TXB (37) 68 #define INT0_HI_MACNET0_UN (38) 69 #define INT0_HI_MACNET0_RL (39) 70 #define INT0_HI_MACNET0_RXF (40) 71 #define INT0_HI_MACNET0_RXB (41) 72 #define INT0_HI_MACNET0_MII (42) 73 #define INT0_HI_MACNET0_LC (43) 74 /* not used 44 */ 75 #define INT0_HI_MACNET0_GRA (45) 76 #define INT0_HI_MACNET0_EBERR (46) 77 #define INT0_HI_MACNET0_BABT (47) 78 #define INT0_HI_MACNET0_BABR (48) 79 #define INT0_HI_MACNET1_TXF (49) 80 #define INT0_HI_MACNET1_TXB (50) 81 #define INT0_HI_MACNET1_UN (51) 82 #define INT0_HI_MACNET1_RL (52) 83 #define INT0_HI_MACNET1_RXF (53) 84 #define INT0_HI_MACNET1_RXB (54) 85 #define INT0_HI_MACNET1_MII (55) 86 #define INT0_HI_MACNET1_LC (56) 87 /* not used 57 */ 88 #define INT0_HI_MACNET1_GRA (58) 89 #define INT0_HI_MACNET1_EBERR (59) 90 #define INT0_HI_MACNET1_BABT (60) 91 #define INT0_HI_MACNET1_BABR (61) 92 #define INT0_HI_SCMIR (62) 93 #define INT0_HI_OW (63) 94 95 #define INT1_LO_CAN0_IFG (0) 96 #define INT1_LO_CAN0_BOFF (1) 97 /* not used 2 */ 98 #define INT1_LO_CAN0_TXRXWRN (3) 99 #define INT1_LO_CAN1_IFG (4) 100 #define INT1_LO_CAN1_BOFF (5) 101 /* not used 6 */ 102 #define INT1_LO_CAN1_TXRXWRN (7) 103 #define INT1_LO_EDMA_16 (8) 104 #define INT1_LO_EDMA_17 (9) 105 #define INT1_LO_EDMA_18 (10) 106 #define INT1_LO_EDMA_19 (11) 107 #define INT1_LO_EDMA_20 (12) 108 #define INT1_LO_EDMA_21 (13) 109 #define INT1_LO_EDMA_22 (14) 110 #define INT1_LO_EDMA_23 (15) 111 #define INT1_LO_EDMA_24 (16) 112 #define INT1_LO_EDMA_25 (17) 113 #define INT1_LO_EDMA_26 (18) 114 #define INT1_LO_EDMA_27 (19) 115 #define INT1_LO_EDMA_28 (20) 116 #define INT1_LO_EDMA_29 (21) 117 #define INT1_LO_EDMA_30 (22) 118 #define INT1_LO_EDMA_31 (23) 119 #define INT1_LO_EDMA_32 (24) 120 #define INT1_LO_EDMA_33 (25) 121 #define INT1_LO_EDMA_34 (26) 122 #define INT1_LO_EDMA_35 (27) 123 #define INT1_LO_EDMA_36 (28) 124 #define INT1_LO_EDMA_37 (29) 125 #define INT1_LO_EDMA_38 (30) 126 #define INT1_LO_EDMA_39 (31) 127 #define INT1_LO_EDMA_40 (32) 128 #define INT1_HI_EDMA_41 (33) 129 #define INT1_HI_EDMA_42 (34) 130 #define INT1_HI_EDMA_43 (35) 131 #define INT1_HI_EDMA_44 (36) 132 #define INT1_HI_EDMA_45 (37) 133 #define INT1_HI_EDMA_46 (38) 134 #define INT1_HI_EDMA_47 (39) 135 #define INT1_HI_EDMA_48 (40) 136 #define INT1_HI_EDMA_49 (41) 137 #define INT1_HI_EDMA_50 (42) 138 #define INT1_HI_EDMA_51 (43) 139 #define INT1_HI_EDMA_52 (44) 140 #define INT1_HI_EDMA_53 (45) 141 #define INT1_HI_EDMA_54 (46) 142 #define INT1_HI_EDMA_55 (47) 143 #define INT1_HI_UART4 (48) 144 #define INT1_HI_UART5 (49) 145 #define INT1_HI_UART6 (50) 146 #define INT1_HI_UART7 (51) 147 #define INT1_HI_UART8 (52) 148 #define INT1_HI_UART9 (53) 149 #define INT1_HI_DSPI1 (54) 150 #define INT1_HI_DSPI2 (55) 151 #define INT1_HI_DSPI3 (56) 152 #define INT1_HI_I2C1 (57) 153 #define INT1_HI_I2C2 (58) 154 #define INT1_HI_I2C3 (59) 155 #define INT1_HI_I2C4 (60) 156 #define INT1_HI_I2C5 (61) 157 158 #define INT2_LO_EDMA56_63 (0) 159 #define INT2_LO_PWM_SM0SR_CF (1) 160 #define INT2_LO_PWM_SM1SR_CF (2) 161 #define INT2_LO_PWM_SM2SR_CF (3) 162 #define INT2_LO_PWM_SM3SR_CF (4) 163 #define INT2_LO_PWM_SM0SR_RF (5) 164 #define INT2_LO_PWM_SM1SR_RF (6) 165 #define INT2_LO_PWM_SM2SR_RF (7) 166 #define INT2_LO_PWM_SM3SR_RF (8) 167 #define INT2_LO_PWM_FSR (9) 168 #define INT2_LO_PWM_SMSR_REF (10) 169 #define INT2_LO_PLL_SR_LOCF (11) 170 #define INT2_LO_PLL_SR_LOLF (12) 171 #define INT2_LO_PIT0_PIF (13) 172 #define INT2_LO_PIT1_PIF (14) 173 #define INT2_LO_PIT2_PIF (15) 174 #define INT2_LO_PIT3_PIF (16) 175 #define INT2_LO_USBOTG_USBSTS (17) 176 #define INT2_LO_USBH_USBSTS (18) 177 /* not used 19-20 */ 178 #define INT2_LO_SSI0 (21) 179 #define INT2_LO_SSI1 (22) 180 #define INT2_LO_NFC (23) 181 /* not used 24-25 */ 182 #define INT2_LO_RTC (26) 183 #define INT2_LO_CCM_UOCSR (27) 184 #define INT2_LO_RNG_EI (28) 185 #define INT2_LO_SIM1_DATA (29) 186 #define INT2_LO_SIM1 (30) 187 #define INT2_LO_SDHC (31) 188 /* not used 32-37 */ 189 #define INT2_HI_L2SW_BERR (38) 190 #define INT2_HI_L2SW_RXB (39) 191 #define INT2_HI_L2SW_RXF (40) 192 #define INT2_HI_L2SW_TXB (41) 193 #define INT2_HI_L2SW_TXF (42) 194 #define INT2_HI_L2SW_QM (43) 195 #define INT2_HI_L2SW_OD0 (44) 196 #define INT2_HI_L2SW_OD1 (45) 197 #define INT2_HI_L2SW_OD2 (46) 198 #define INT2_HI_L2SW_LRN (47) 199 #define INT2_HI_MACNET0_TS (48) 200 #define INT2_HI_MACNET0_WAKE (49) 201 #define INT2_HI_MACNET0_PLR (50) 202 /* not used 51-54 */ 203 #define INT2_HI_MACNET1_TS (51) 204 #define INT2_HI_MACNET1_WAKE (52) 205 #define INT2_HI_MACNET1_PLR (53) 206 207 /* Serial Boot Facility (SBF) */ 208 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) 209 #define SBF_SBFCR_FR (0x0010) 210 211 /* Reset Controller Module (RCM) */ 212 #define RCM_RCR_SOFTRST (0x80) 213 #define RCM_RCR_FRCRSTOUT (0x40) 214 215 #define RCM_RSR_SOFT (0x20) 216 #define RCM_RSR_LOC (0x10) 217 #define RCM_RSR_POR (0x08) 218 #define RCM_RSR_EXT (0x04) 219 #define RCM_RSR_WDR_CORE (0x02) 220 #define RCM_RSR_LOL (0x01) 221 222 /* Chip Configuration Module (CCM) */ 223 #define CCM_CCR_BOOTMOD (0xC000) 224 #define CCM_CCR_PLLMULT (0x0FC0) 225 #define CCM_CCR_BOOTPS (0x0030) 226 #define CCM_CCR_BOOTPS_32 (0x0000) 227 #define CCM_CCR_BOOTPS_16 (0x0020) 228 #define CCM_CCR_BOOTPS_8 (0x0010) 229 #define CCM_CCR_BOOTPS_ (0x0000) 230 #define CCM_CCR_ALESEL (0x0008) 231 #define CCM_CCR_OSCMOD (0x0004) 232 #define CCM_CCR_PLLMOD (0x0002) 233 #define CCM_CCR_BOOTMEM (0x0001) 234 235 #define CCM_CIR_PIN_MASK (0xFFC0) 236 #define CCM_CIR_PRN_MASK (0x003F) 237 #define CCM_CIR_PIN_MCF54410 (0x9F<<6) 238 #define CCM_CIR_PIN_MCF54415 (0xA0<<6) 239 #define CCM_CIR_PIN_MCF54416 (0xA1<<6) 240 #define CCM_CIR_PIN_MCF54417 (0xA2<<6) 241 #define CCM_CIR_PIN_MCF54418 (0xA3<<6) 242 243 #define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14) 244 #define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF) 245 #define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000) 246 #define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000) 247 #define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000) 248 #define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000) 249 #define CCM_MISCCR_LIMP (0x1000) 250 #define CCM_MISCCR_BME (0x0800) 251 #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) 252 #define CCM_MISCCR_BMT_65536 (0) 253 #define CCM_MISCCR_BMT_32768 (1) 254 #define CCM_MISCCR_BMT_16384 (2) 255 #define CCM_MISCCR_BMT_8192 (3) 256 #define CCM_MISCCR_BMT_4096 (4) 257 #define CCM_MISCCR_BMT_2048 (5) 258 #define CCM_MISCCR_BMT_1024 (6) 259 #define CCM_MISCCR_BMT_512 (7) 260 #define CCM_MISCCR_SDHCSRC (0x0040) 261 #define CCM_MISCCR_SSI1SRC (0x0020) 262 #define CCM_MISCCR_SSI0SRC (0x0010) 263 #define CCM_MISCCR_USBHOC (0x0008) 264 #define CCM_MISCCR_USBOOC (0x0004) 265 #define CCM_MISCCR_USBPUE (0x0002) 266 #define CCM_MISCCR_USBSRC (0x0001) 267 268 #define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8) 269 #define CCM_CDRH_SSI0DIV_MASK (0x00FF) 270 #define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF)) 271 #define CCM_CDRH_SSI1DIV_MASK (0xFF00) 272 #define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8) 273 #define CCM_CDRL_LPDIV_MASK (0xFF0F) 274 #define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x) 275 276 #define CCM_UOCSR_DPPD (0x2000) 277 #define CCM_UOCSR_DMPD (0x1000) 278 #define CCM_UOCSR_DRV_VBUS (0x0800) 279 #define CCM_UOCSR_CRG_VBUS (0x0400) 280 #define CCM_UOCSR_DCR_VBUS (0x0200) 281 #define CCM_UOCSR_DPPU (0x0100) 282 #define CCM_UOCSR_AVLD (0x0080) 283 #define CCM_UOCSR_BVLD (0x0040) 284 #define CCM_UOCSR_VVLD (0x0020) 285 #define CCM_UOCSR_SEND (0x0010) 286 #define CCM_UOCSR_PWRFLT (0x0008) 287 #define CCM_UOCSR_WKUP (0x0004) 288 #define CCM_UOCSR_UOMIE (0x0002) 289 #define CCM_UOCSR_XPDE (0x0001) 290 291 #define CCM_UHCSR_DRV_VBUS (0x0010) 292 #define CCM_UHCSR_PWRFLT (0x0008) 293 #define CCM_UHCSR_WKUP (0x0004) 294 #define CCM_UHCSR_UOMIE (0x0002) 295 #define CCM_UHCSR_XPDE (0x0001) 296 297 #define CCM_MISCCR3_TMR_ENET (0x1000) 298 #define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8) 299 #define CCM_MISCCR3_ENETCLK_MASK (0xF8FF) 300 #define CCM_MISCCR3_ENETCLK_MII (0x0700) 301 #define CCM_MISCCR3_ENETCLK_OSC (0x0600) 302 #define CCM_MISCCR3_ENETCLK_USB (0x0500) 303 #define CCM_MISCCR3_ENETCLK_TMR3 (0x0400) 304 #define CCM_MISCCR3_ENETCLK_TMR2 (0x0300) 305 #define CCM_MISCCR3_ENETCLK_TMR1 (0x0200) 306 #define CCM_MISCCR3_ENETCLK_TMR0 (0x0100) 307 #define CCM_MISCCR3_ENETCLK_INTBUS (0x0000) 308 309 #define CCM_MISCCR2_EXTCLKBYP (0x8000) 310 #define CCM_MISCCR2_DDR2CLK (0x4000) 311 #define CCM_MISCCR2_RGPIO_HALF (0x2000) 312 #define CCM_MISCCR2_SWTSCR (0x1000) 313 #define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8) 314 #define CCM_MISCCR2_PLLMODE_MASK (0xF8FF) 315 #define CCM_MISCCR2_DCCBYP (0x0080) 316 #define CCM_MISCCR2_DAC1SEL (0x0040) 317 #define CCM_MISCCR2_DAC0SEL (0x0020) 318 #define CCM_MISCCR2_ADCEN (0x0010) 319 #define CCM_MISCCR2_ADC7SEL (0x0008) 320 #define CCM_MISCCR2_ADC3SEL (0x0004) 321 #define CCM_MISCCR2_FBHALF (0x0002) 322 #define CCM_MISCCR2_ULPI (0x0001) 323 324 #define CCM_FNACR_PCR(x) (((x)&0x0F)<<24) 325 #define CCM_FNACR_PCR_MASK (0xF0FFFFFF) 326 #define CCM_FNACR_MCC(x) ((x)&0xFFFF) 327 #define CCM_FNACR_MCC_MASK (0xFFFF0000) 328 329 /* General Purpose I/O Module (GPIO) */ 330 #define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6) 331 #define GPIO_PAR_FBCTL_ALE_MASK (0x3F) 332 #define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0) 333 #define GPIO_PAR_FBCTL_ALE_FB_TS (0x80) 334 #define GPIO_PAR_FBCTL_ALE_GPIO (0x00) 335 #define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4) 336 #define GPIO_PAR_FBCTL_OE_MASK (0xCF) 337 #define GPIO_PAR_FBCTL_OE_FB_OE (0x30) 338 #define GPIO_PAR_FBCTL_OE_FB_TBST (0x20) 339 #define GPIO_PAR_FBCTL_OE_NFC_RE (0x20) 340 #define GPIO_PAR_FBCTL_OE_GPIO (0x00) 341 #define GPIO_PAR_FBCTL_FBCLK (0x08) 342 #define GPIO_PAR_FBCTL_RW (0x04) 343 #define GPIO_PAR_FBCTL_TA(x) ((x)&3) 344 #define GPIO_PAR_FBCTL_TA_MASK (0xFC) 345 #define GPIO_PAR_FBCTL_TA_TA (0x03) 346 #define GPIO_PAR_FBCTL_TA_NFC_RB (0x01) 347 #define GPIO_PAR_FBCTL_TA_GPIO (0x00) 348 349 #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) 350 #define GPIO_PAR_BE_BE3_MASK (0x3F) 351 #define GPIO_PAR_BE_BE3_BE3 (0xC0) 352 #define GPIO_PAR_BE_BE3_CS3 (0x80) 353 #define GPIO_PAR_BE_BE3_FB_A1 (0x40) 354 #define GPIO_PAR_BE_BE3_NFC_ALE (0x40) 355 #define GPIO_PAR_BE_BE3_GPIO (0x00) 356 #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) 357 #define GPIO_PAR_BE_BE2_MASK (0xCF) 358 #define GPIO_PAR_BE_BE2_BE2 (0x30) 359 #define GPIO_PAR_BE_BE2_CS2 (0x20) 360 #define GPIO_PAR_BE_BE2_FB_A0 (0x10) 361 #define GPIO_PAR_BE_BE2_NFC_CLE (0x10) 362 #define GPIO_PAR_BE_BE2_GPIO (0x00) 363 #define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2) 364 #define GPIO_PAR_BE_BE1_MASK (0xF3) 365 #define GPIO_PAR_BE_BE1_BE1 (0x0C) 366 #define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08) 367 #define GPIO_PAR_BE_BE1_GPIO (0x00) 368 #define GPIO_PAR_BE_BS0(x) ((x)&0x03) 369 #define GPIO_PAR_BE_BE0_MASK (0xFC) 370 #define GPIO_PAR_BE_BE0_BE0 (0x03) 371 #define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02) 372 #define GPIO_PAR_BE_BE0_GPIO (0x00) 373 374 #define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6) 375 #define GPIO_PAR_CS_CS5_MASK (0x3F) 376 #define GPIO_PAR_CS_CS5_CS5 (0xC0) 377 #define GPIO_PAR_CS_CS5_DACK1 (0x80) 378 #define GPIO_PAR_CS_CS5_GPIO (0x00) 379 #define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4) 380 #define GPIO_PAR_CS_CS4_MASK (0xCF) 381 #define GPIO_PAR_CS_CS4_CS4 (0x30) 382 #define GPIO_PAR_CS_CS4_DREQ1 (0x20) 383 #define GPIO_PAR_CS_CS4_GPIO (0x00) 384 #define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2) 385 #define GPIO_PAR_CS_CS1_MASK (0xF3) 386 #define GPIO_PAR_CS_CS1_CS1 (0x0C) 387 #define GPIO_PAR_CS_CS1_NFC_CE (0x04) 388 #define GPIO_PAR_CS_CS1_GPIO (0x00) 389 #define GPIO_PAR_CS_CS0_CS0 (0x01) 390 391 #define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6) 392 #define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F) 393 #define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0) 394 #define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80) 395 #define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40) 396 #define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00) 397 #define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4) 398 #define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF) 399 #define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30) 400 #define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20) 401 #define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10) 402 #define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00) 403 #define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2) 404 #define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3) 405 #define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C) 406 #define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08) 407 #define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04) 408 #define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00) 409 #define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03) 410 #define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC) 411 #define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03) 412 #define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02) 413 #define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01) 414 #define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00) 415 416 #define GPIO_PAR_IRQH_IRQ7 (0x10) 417 #define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2) 418 #define GPIO_PAR_IRQH_IRQ4_MASK (0xF3) 419 #define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C) 420 #define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08) 421 #define GPIO_PAR_IRQH_IRQ4_GPIO (0x00) 422 #define GPIO_PAR_IRQH_IRQ1 (0x03) 423 424 #define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6) 425 #define GPIO_PAR_IRQL_IRQ6_MASK (0x3F) 426 #define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0) 427 #define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40) 428 #define GPIO_PAR_IRQL_IRQ6_GPIO (0x00) 429 #define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4) 430 #define GPIO_PAR_IRQL_IRQ3_MASK (0xCF) 431 #define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30) 432 #define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20) 433 #define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10) 434 #define GPIO_PAR_IRQL_IRQ3_GPIO (0x00) 435 #define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2) 436 #define GPIO_PAR_IRQL_IRQ2_MASK (0xF3) 437 #define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C) 438 #define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08) 439 #define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04) 440 #define GPIO_PAR_IRQL_IRQ2_GPIO (0x00) 441 442 #define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6) 443 #define GPIO_PAR_DSPI0_SIN_MASK (0x3F) 444 #define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0) 445 #define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0) 446 #define GPIO_PAR_DSPI0_SIN_U3RXD (0x80) 447 #define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40) 448 #define GPIO_PAR_DSPI0_SIN_GPIO (0x00) 449 #define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4) 450 #define GPIO_PAR_DSPI0_SOUT_MASK (0xCF) 451 #define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30) 452 #define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30) 453 #define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20) 454 #define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10) 455 #define GPIO_PAR_DSPI0_SOUT_GPIO (0x00) 456 #define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2) 457 #define GPIO_PAR_DSPI0_SCK_MASK (0xF3) 458 #define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C) 459 #define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C) 460 #define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08) 461 #define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04) 462 #define GPIO_PAR_DSPI0_SCK_GPIO (0x00) 463 #define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03) 464 #define GPIO_PAR_DSPI0_PCS0_MASK (0xFC) 465 #define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03) 466 #define GPIO_PAR_DSPI0_PCS0_SS (0x03) 467 #define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02) 468 #define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01) 469 #define GPIO_PAR_DSPI0_PCS0_GPIO (0x00) 470 471 #define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80) 472 #define GPIO_PAR_DSPIOW_SBF_CS (0x80) 473 #define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4) 474 #define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF) 475 #define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30) 476 #define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20) 477 #define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00) 478 479 #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) 480 #define GPIO_PAR_TIMER_T3IN_MASK (0x3F) 481 #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) 482 #define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0) 483 #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) 484 #define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40) 485 #define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40) 486 #define GPIO_PAR_TIMER_T3IN_GPIO (0x00) 487 #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) 488 #define GPIO_PAR_TIMER_T2IN_MASK (0xCF) 489 #define GPIO_PAR_TIMER_T2IN_T2IN (0x30) 490 #define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30) 491 #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) 492 #define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10) 493 #define GPIO_PAR_TIMER_T2IN_GPIO (0x00) 494 #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) 495 #define GPIO_PAR_TIMER_T1IN_MASK (0xF3) 496 #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) 497 #define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C) 498 #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) 499 #define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04) 500 #define GPIO_PAR_TIMER_T1IN_GPIO (0x00) 501 #define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03) 502 #define GPIO_PAR_TIMER_T0IN_MASK (0xFC) 503 #define GPIO_PAR_TIMER_T0IN_T0IN (0x03) 504 #define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03) 505 #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) 506 #define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01) 507 #define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01) 508 #define GPIO_PAR_TIMER_T0IN_GPIO (0x00) 509 510 #define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6) 511 #define GPIO_PAR_UART2_U2CTS_MASK (0x3F) 512 #define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0) 513 #define GPIO_PAR_UART2_U2CTS_U6TXD (0x80) 514 #define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40) 515 #define GPIO_PAR_UART2_U2CTS_GPIO (0x00) 516 #define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4) 517 #define GPIO_PAR_UART2_U2RTS_MASK (0xCF) 518 #define GPIO_PAR_UART2_U2RTS_U2RTS (0x30) 519 #define GPIO_PAR_UART2_U2RTS_U6RXD (0x20) 520 #define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10) 521 #define GPIO_PAR_UART2_U2RTS_GPIO (0x00) 522 #define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2) 523 #define GPIO_PAR_UART2_U2RXD_MASK (0xF3) 524 #define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C) 525 #define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08) 526 #define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04) 527 #define GPIO_PAR_UART2_U2RXD_GPIO (0x00) 528 #define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03) 529 #define GPIO_PAR_UART2_U2TXD_MASK (0xFC) 530 #define GPIO_PAR_UART2_U2TXD_U2TXD (0x03) 531 #define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02) 532 #define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01) 533 #define GPIO_PAR_UART2_U2TXD_GPIO (0x00) 534 535 #define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6) 536 #define GPIO_PAR_UART1_U1CTS_MASK (0x3F) 537 #define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0) 538 #define GPIO_PAR_UART1_U1CTS_U5TXD (0x80) 539 #define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40) 540 #define GPIO_PAR_UART1_U1CTS_GPIO (0x00) 541 #define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4) 542 #define GPIO_PAR_UART1_U1RTS_MASK (0xCF) 543 #define GPIO_PAR_UART1_U1RTS_U1RTS (0x30) 544 #define GPIO_PAR_UART1_U1RTS_U5RXD (0x20) 545 #define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10) 546 #define GPIO_PAR_UART1_U1RTS_GPIO (0x00) 547 #define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2) 548 #define GPIO_PAR_UART1_U1RXD_MASK (0xF3) 549 #define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C) 550 #define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08) 551 #define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04) 552 #define GPIO_PAR_UART1_U1RXD_GPIO (0x00) 553 #define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03) 554 #define GPIO_PAR_UART1_U1TXD_MASK (0xFC) 555 #define GPIO_PAR_UART1_U1TXD_U1TXD (0x03) 556 #define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02) 557 #define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01) 558 #define GPIO_PAR_UART1_U1TXD_GPIO (0x00) 559 560 #define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6) 561 #define GPIO_PAR_UART0_U0CTS_MASK (0x3F) 562 #define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0) 563 #define GPIO_PAR_UART0_U0CTS_U4TXD (0x80) 564 #define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40) 565 #define GPIO_PAR_UART0_U0CTS_GPIO (0x00) 566 #define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4) 567 #define GPIO_PAR_UART0_U0RTS_MASK (0xCF) 568 #define GPIO_PAR_UART0_U0RTS_U0RTS (0x30) 569 #define GPIO_PAR_UART0_U0RTS_U4RXD (0x20) 570 #define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10) 571 #define GPIO_PAR_UART0_U0RTS_GPIO (0x00) 572 #define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2) 573 #define GPIO_PAR_UART0_U0RXD_MASK (0xF3) 574 #define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C) 575 #define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08) 576 #define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04) 577 #define GPIO_PAR_UART0_U0RXD_GPIO (0x00) 578 #define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03) 579 #define GPIO_PAR_UART0_U0TXD_MASK (0xFC) 580 #define GPIO_PAR_UART0_U0TXD_U0TXD (0x03) 581 #define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02) 582 #define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01) 583 #define GPIO_PAR_UART0_U0TXD_GPIO (0x00) 584 585 #define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6) 586 #define GPIO_PAR_SDHCH_DAT3_MASK (0x3F) 587 #define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0) 588 #define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80) 589 #define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40) 590 #define GPIO_PAR_SDHCH_DAT3_GPIO (0x00) 591 #define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4) 592 #define GPIO_PAR_SDHCH_DAT2_MASK (0xCF) 593 #define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30) 594 #define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20) 595 #define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10) 596 #define GPIO_PAR_SDHCH_DAT2_GPIO (0x00) 597 #define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2) 598 #define GPIO_PAR_SDHCH_DAT1_MASK (0xF3) 599 #define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C) 600 #define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08) 601 #define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04) 602 #define GPIO_PAR_SDHCH_DAT1_GPIO (0x00) 603 #define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03) 604 #define GPIO_PAR_SDHCH_DAT0_MASK (0xFC) 605 #define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03) 606 #define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02) 607 #define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01) 608 #define GPIO_PAR_SDHCH_DAT0_GPIO (0x00) 609 610 #define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2) 611 #define GPIO_PAR_SDHCL_CMD_MASK (0xF3) 612 #define GPIO_PAR_SDHCL_CMD_CMD (0x0C) 613 #define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08) 614 #define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04) 615 #define GPIO_PAR_SDHCL_CMD_GPIO (0x00) 616 #define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03) 617 #define GPIO_PAR_SDHCL_CLK_MASK (0xFC) 618 #define GPIO_PAR_SDHCL_CLK_CLK (0x03) 619 #define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02) 620 #define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01) 621 #define GPIO_PAR_SDHCL_CLK_GPIO (0x00) 622 623 #define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6) 624 #define GPIO_PAR_SIMP0H_DAT_MASK (0x3F) 625 #define GPIO_PAR_SIMP0H_DAT_DAT (0xC0) 626 #define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80) 627 #define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40) 628 #define GPIO_PAR_SIMP0H_DAT_GPIO (0x00) 629 #define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4) 630 #define GPIO_PAR_SIMP0H_VEN_MASK (0xCF) 631 #define GPIO_PAR_SIMP0H_VEN_VEN (0x30) 632 #define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20) 633 #define GPIO_PAR_SIMP0H_VEN_GPIO (0x00) 634 #define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2) 635 #define GPIO_PAR_SIMP0H_RST_MASK (0xF3) 636 #define GPIO_PAR_SIMP0H_RST_RST (0x0C) 637 #define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08) 638 #define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04) 639 #define GPIO_PAR_SIMP0H_RST_GPIO (0x00) 640 #define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03) 641 #define GPIO_PAR_SIMP0H_PD_MASK (0xFC) 642 #define GPIO_PAR_SIMP0H_PD_PD (0x03) 643 #define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02) 644 #define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01) 645 #define GPIO_PAR_SIMP0H_PD_GPIO (0x00) 646 647 #define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03) 648 #define GPIO_PAR_SIMP0L_CLK_MASK (0xFC) 649 #define GPIO_PAR_SIMP0L_CLK_CLK (0x03) 650 #define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02) 651 #define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01) 652 #define GPIO_PAR_SIMP0L_CLK_GPIO (0x00) 653 654 #define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6) 655 #define GPIO_PAR_SSI0H_RXD_MASK (0x3F) 656 #define GPIO_PAR_SSI0H_RXD_RXD (0xC0) 657 #define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80) 658 #define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40) 659 #define GPIO_PAR_SSI0H_RXD_GPIO (0x00) 660 #define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4) 661 #define GPIO_PAR_SSI0H_TXD_MASK (0xCF) 662 #define GPIO_PAR_SSI0H_TXD_TXD (0x30) 663 #define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20) 664 #define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10) 665 #define GPIO_PAR_SSI0H_TXD_GPIO (0x00) 666 #define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2) 667 #define GPIO_PAR_SSI0H_FS_MASK (0xF3) 668 #define GPIO_PAR_SSI0H_FS_FS (0x0C) 669 #define GPIO_PAR_SSI0H_FS_U7TXD (0x08) 670 #define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04) 671 #define GPIO_PAR_SSI0H_FS_GPIO (0x00) 672 #define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03) 673 #define GPIO_PAR_SSI0H_MCLK_MASK (0xFC) 674 #define GPIO_PAR_SSI0H_MCLK_MCLK (0x03) 675 #define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02) 676 #define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01) 677 #define GPIO_PAR_SSI0H_MCLK_GPIO (0x00) 678 679 #define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03) 680 #define GPIO_PAR_SSI0L_BCLK_MASK (0xFC) 681 #define GPIO_PAR_SSI0L_BCLK_BCLK (0x03) 682 #define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02) 683 #define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01) 684 #define GPIO_PAR_SSI0L_BCLK_GPIO (0x00) 685 686 #define GPIO_PAR_DEBUGH1_DAT3 (0x40) 687 #define GPIO_PAR_DEBUGH1_DAT2 (0x10) 688 #define GPIO_PAR_DEBUGH1_DAT1 (0x04) 689 #define GPIO_PAR_DEBUGH1_DAT0 (0x01) 690 691 #define GPIO_PAR_DEBUGH0_PST3 (0x40) 692 #define GPIO_PAR_DEBUGH0_PST2 (0x10) 693 #define GPIO_PAR_DEBUGH0_PST1 (0x04) 694 #define GPIO_PAR_DEBUGH0_PST0 (0x01) 695 696 #define GPIO_PODR_G4_VAL (0x01 << 4) 697 #define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL) 698 #define GPIO_PDDR_G4_OUTPUT (0x01 << 4) 699 #define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT) 700 701 #define GPIO_PAR_DEBUGL_ALLPST (0x01) 702 703 #define GPIO_PAR_FEC_FEC(x) ((x)&0x0F) 704 #define GPIO_PAR_FEC_FEC_MASK (0xF0) 705 #define GPIO_PAR_FEC_FEC_GPIO (0x0D) 706 #define GPIO_PAR_FEC_FEC_RMII1 (0x0C) 707 #define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B) 708 #define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A) 709 #define GPIO_PAR_FEC_FEC_RMII0 (0x09) 710 #define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08) 711 #define GPIO_PAR_FEC_FEC_RMII0FUL (0x07) 712 #define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06) 713 #define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */ 714 /* Both 0&1: MDC, MDIO, COL & TXER - GPIO */ 715 #define GPIO_PAR_FEC_FEC_RMII0_1 (0x04) 716 #define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03) 717 #define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */ 718 #define GPIO_PAR_FEC_FEC_MIIFUL (0x00) 719 720 721 /* TC: Need to edit here.... */ 722 723 /* Mode Select Control */ 724 #define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03) 725 #define GPIO_MSCR_SDRAM_MSC_MASK (0xFC) 726 727 /* Slew Rate Control */ 728 729 #define GPIO_SRCR_FB3_FB3(x) ((x)&0x03) 730 #define GPIO_SRCR_FB3_FB3_MASK (0xFC) 731 732 #define GPIO_SRCR_FB2_FB2(x) ((x)&0x03) 733 #define GPIO_SRCR_FB2_FB2_MASK (0xFC) 734 735 #define GPIO_SRCR_FB1_FB1(x) ((x)&0x03) 736 #define GPIO_SRCR_FB1_FB1_MASK (0xFC) 737 738 #define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2) 739 #define GPIO_SRCR_FB4_FB5_MASK (0xF3) 740 #define GPIO_SRCR_FB4_FB4(x) ((x)&0x03) 741 #define GPIO_SRCR_FB4_FB4_MASK (0xFC) 742 743 #define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4) 744 #define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF) 745 #define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03) 746 #define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC) 747 748 #define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2) 749 #define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3) 750 #define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03) 751 #define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC) 752 753 #define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03) 754 #define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC) 755 756 #define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6) 757 #define GPIO_SRCR_TIMER_TMR3_MASK (0x3F) 758 #define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4) 759 #define GPIO_SRCR_TIMER_TMR2_MASK (0xCF) 760 #define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2) 761 #define GPIO_SRCR_TIMER_TMR1_MASK (0xF3) 762 #define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03) 763 #define GPIO_SRCR_TIMER_TMR0_MASK (0xFC) 764 765 #define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4) 766 #define GPIO_SRCR_UART_U2_MASK (0xCF) 767 #define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2) 768 #define GPIO_SRCR_UART_U1_MASK (0xF3) 769 #define GPIO_SRCR_UART_U0(x) ((x)&0x03) 770 #define GPIO_SRCR_UART_U0_MASK (0xFC) 771 772 #define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2) 773 #define GPIO_SRCR_FEC_RMII0_MASK (0xF3) 774 #define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03) 775 #define GPIO_SRCR_FEC_RMII1_MASK (0xFC) 776 777 #define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03) 778 #define GPIO_SRCR_SDHC_SDHC_MASK (0xFC) 779 780 #define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03) 781 #define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC) 782 783 #define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03) 784 #define GPIO_SRCR_SSI0_SSI0_MASK (0xFC) 785 786 #define GPIO_PCR_URTS_U2 (0x0004) 787 #define GPIO_PCR_URTS_U1 (0x0002) 788 #define GPIO_PCR_URTS_U0 (0x0001) 789 790 #define GPIO_PCR_UCTS_U2 (0x0004) 791 #define GPIO_PCR_UCTS_U1 (0x0002) 792 #define GPIO_PCR_UCTS_U0 (0x0001) 793 794 #define GPIO_UTXD_WOM_U9 (0x0200) 795 #define GPIO_UTXD_WOM_U8 (0x0100) 796 #define GPIO_UTXD_WOM_U7 (0x0080) 797 #define GPIO_UTXD_WOM_U6 (0x0040) 798 #define GPIO_UTXD_WOM_U5 (0x0020) 799 #define GPIO_UTXD_WOM_U4 (0x0010) 800 #define GPIO_UTXD_WOM_U3 (0x0008) 801 #define GPIO_UTXD_WOM_U2 (0x0004) 802 #define GPIO_UTXD_WOM_U1 (0x0002) 803 #define GPIO_UTXD_WOM_U0 (0x0001) 804 805 #define GPIO_URXD_WOM_U9(x) (((x)&3)<<18) 806 #define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF) 807 #define GPIO_URXD_WOM_U8(x) (((x)&3)<<16) 808 #define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF) 809 #define GPIO_URXD_WOM_U7(x) (((x)&3)<<14) 810 #define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF) 811 #define GPIO_URXD_WOM_U6(x) (((x)&3)<<12) 812 #define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF) 813 #define GPIO_URXD_WOM_U5(x) (((x)&3)<<10) 814 #define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF) 815 #define GPIO_URXD_WOM_U4(x) (((x)&3)<<8) 816 #define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF) 817 #define GPIO_URXD_WOM_U3(x) (((x)&3)<<6) 818 #define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F) 819 #define GPIO_URXD_WOM_U2(x) (((x)&3)<<4) 820 #define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF) 821 #define GPIO_URXD_WOM_U1(x) (((x)&3)<<2) 822 #define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3) 823 #define GPIO_URXD_WOM_U0(x) ((x)&3) 824 #define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC) 825 826 #define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27) 827 #define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF) 828 #define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22) 829 #define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF) 830 #define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15) 831 #define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF) 832 #define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10) 833 #define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF) 834 #define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3) 835 #define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07) 836 #define GPIO_HCR1_PB2_0(x) ((x)&7) 837 #define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8) 838 839 #define GPIO_HCR0_PK3 (0x00000400) 840 #define GPIO_HCR0_PK0 (0x00000200) 841 #define GPIO_HCR0_PD2_0(x) (((x)&7)<<6) 842 #define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F) 843 #define GPIO_HCR0_PE7 (0x00000020) 844 #define GPIO_HCR0_PH7_3(x) ((x)&0x1F) 845 #define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0) 846 847 /* SDRAM Controller (SDRAMC) */ 848 849 /* Phase Locked Loop (PLL) */ 850 #define PLL_CR_LOCIRQ (0x00040000) 851 #define PLL_CR_LOCRE (0x00020000) 852 #define PLL_CR_LOCEN (0x00010000) 853 #define PLL_CR_LOLIRQ (0x00004000) 854 #define PLL_CR_LOLRE (0x00002000) 855 #define PLL_CR_LOLEN (0x00001000) 856 #define PLL_CR_REFDIV(x) (((x)&7)<<8) 857 #define PLL_CR_REFDIV_MASK (0xFFFFF8FF) 858 #define PLL_CR_FBKDIV(x) ((x)&0x3F) 859 #define PLL_CR_FBKDIV_MASK (0xFFFFFFC0) 860 #define PLL_CR_FBKDIV_BITS (0x3F) 861 862 #define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21) 863 #define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF) 864 #define PLL_DR_OUTDIV5_BITS (0x03E00000) 865 #define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16) 866 #define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF) 867 #define PLL_DR_OUTDIV4_BITS (0x001F0000) 868 #define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10) 869 #define PLL_DR_OUTDIV3_MASK (0xFFFF83FF) 870 #define PLL_DR_OUTDIV3_BITS (0x00007C00) 871 #define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5) 872 #define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F) 873 #define PLL_DR_OUTDIV2_BITS (0x000003E0) 874 #define PLL_DR_OUTDIV1(x) ((x)&0x1F) 875 #define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0) 876 #define PLL_DR_OUTDIV1_BITS (0x0000001F) 877 878 #define PLL_SR_LOCF (0x00000200) 879 #define PLL_SR_LOC (0x00000100) 880 #define PLL_SR_LOLF (0x00000040) 881 #define PLL_SR_LOCKS (0x00000020) 882 #define PLL_SR_LOCK (0x00000010) 883 #define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */ 884 #define PLL_SR_MODE(x) ((x)&7) 885 #define PLL_SR_MODE_MASK (0xFFFFFFF8) 886 887 #endif /* __MCF5441X__ */ 888