1 /* 2 * MCF5275 Internal Memory Map 3 * 4 * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com) 5 * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __M5275_H__ 27 #define __M5275_H__ 28 29 /* 30 * Define the 5275 SIM register set addresses. These are similar, 31 * but not quite identical to the 5282 registers and offsets. 32 */ 33 #define MCF_GPIO_PAR_UART 0x10007c 34 #define UART0_ENABLE_MASK 0x000f 35 #define UART1_ENABLE_MASK 0x00f0 36 #define UART2_ENABLE_MASK 0x3f00 37 38 #define MCF_GPIO_PAR_FECI2C 0x100082 39 #define PAR_SDA_ENABLE_MASK 0x0003 40 #define PAR_SCL_ENABLE_MASK 0x000c 41 42 #define MCFSIM_WRRR 0x140000 43 #define MCFSIM_SDCR 0x40 44 45 /********************************************************************* 46 * SDRAM Controller (SDRAMC) 47 *********************************************************************/ 48 49 /* Register read/write macros */ 50 #define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040])) 51 #define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044])) 52 #define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) 53 #define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) 54 #define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) 55 #define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058])) 56 #define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) 57 #define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C])) 58 59 /* Bit definitions and macros for MCF_SDRAMC_SDMR */ 60 #define MCF_SDRAMC_SDMR_CMD (0x00010000) 61 #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) 62 #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) 63 #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) 64 #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) 65 66 /* Bit definitions and macros for MCF_SDRAMC_SDCR */ 67 #define MCF_SDRAMC_SDCR_IPALL (0x00000002) 68 #define MCF_SDRAMC_SDCR_IREF (0x00000004) 69 #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) 70 #define MCF_SDRAMC_SDCR_DQP_BP (0x00008000) 71 #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) 72 #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) 73 #define MCF_SDRAMC_SDCR_REF (0x10000000) 74 #define MCF_SDRAMC_SDCR_CKE (0x40000000) 75 #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) 76 77 /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ 78 #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) 79 #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) 80 #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) 81 #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) 82 #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) 83 #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) 84 #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) 85 86 /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ 87 #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) 88 #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) 89 #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) 90 #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) 91 92 /* Bit definitions and macros for MCF_SDRAMC_SDBARn */ 93 #define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18) 94 #define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000) 95 96 /* Bit definitions and macros for MCF_SDRAMC_SDMRn */ 97 #define MCF_SDRAMC_SDMRn_V (0x00000001) 98 #define MCF_SDRAMC_SDMRn_WP (0x00000080) 99 #define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18) 100 #define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000) 101 #define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000) 102 #define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000) 103 #define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000) 104 #define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000) 105 #define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000) 106 #define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000) 107 #define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000) 108 #define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000) 109 #define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000) 110 #define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000) 111 #define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000) 112 #define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000) 113 #define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000) 114 #define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000) 115 #define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000) 116 #define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000) 117 #define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000) 118 #define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000) 119 120 /********************************************************************* 121 * Interrupt Controller (INTC) 122 ********************************************************************/ 123 #define INT0_LO_RSVD0 (0) 124 #define INT0_LO_EPORT1 (1) 125 #define INT0_LO_EPORT2 (2) 126 #define INT0_LO_EPORT3 (3) 127 #define INT0_LO_EPORT4 (4) 128 #define INT0_LO_EPORT5 (5) 129 #define INT0_LO_EPORT6 (6) 130 #define INT0_LO_EPORT7 (7) 131 #define INT0_LO_SCM (8) 132 #define INT0_LO_DMA0 (9) 133 #define INT0_LO_DMA1 (10) 134 #define INT0_LO_DMA2 (11) 135 #define INT0_LO_DMA3 (12) 136 #define INT0_LO_UART0 (13) 137 #define INT0_LO_UART1 (14) 138 #define INT0_LO_UART2 (15) 139 #define INT0_LO_RSVD1 (16) 140 #define INT0_LO_I2C (17) 141 #define INT0_LO_QSPI (18) 142 #define INT0_LO_DTMR0 (19) 143 #define INT0_LO_DTMR1 (20) 144 #define INT0_LO_DTMR2 (21) 145 #define INT0_LO_DTMR3 (22) 146 #define INT0_LO_FEC0_TXF (23) 147 #define INT0_LO_FEC0_TXB (24) 148 #define INT0_LO_FEC0_UN (25) 149 #define INT0_LO_FEC0_RL (26) 150 #define INT0_LO_FEC0_RXF (27) 151 #define INT0_LO_FEC0_RXB (28) 152 #define INT0_LO_FEC0_MII (29) 153 #define INT0_LO_FEC0_LC (30) 154 #define INT0_LO_FEC0_HBERR (31) 155 #define INT0_HI_FEC0_GRA (32) 156 #define INT0_HI_FEC0_EBERR (33) 157 #define INT0_HI_FEC0_BABT (34) 158 #define INT0_HI_FEC0_BABR (35) 159 #define INT0_HI_PIT0 (36) 160 #define INT0_HI_PIT1 (37) 161 #define INT0_HI_PIT2 (38) 162 #define INT0_HI_PIT3 (39) 163 #define INT0_HI_RNG (40) 164 #define INT0_HI_SKHA (41) 165 #define INT0_HI_MDHA (42) 166 #define INT0_HI_USB (43) 167 #define INT0_HI_USB_EP0 (44) 168 #define INT0_HI_USB_EP1 (45) 169 #define INT0_HI_USB_EP2 (46) 170 #define INT0_HI_USB_EP3 (47) 171 /* 48-63 Reserved */ 172 173 /* 0-22 Reserved */ 174 #define INT1_LO_FEC1_TXF (23) 175 #define INT1_LO_FEC1_TXB (24) 176 #define INT1_LO_FEC1_UN (25) 177 #define INT1_LO_FEC1_RL (26) 178 #define INT1_LO_FEC1_RXF (27) 179 #define INT1_LO_FEC1_RXB (28) 180 #define INT1_LO_FEC1_MII (29) 181 #define INT1_LO_FEC1_LC (30) 182 #define INT1_LO_FEC1_HBERR (31) 183 #define INT1_HI_FEC1_GRA (32) 184 #define INT1_HI_FEC1_EBERR (33) 185 #define INT1_HI_FEC1_BABT (34) 186 #define INT1_HI_FEC1_BABR (35) 187 /* 36-63 Reserved */ 188 189 /* Bit definitions and macros for RCR */ 190 #define RCM_RCR_FRCRSTOUT (0x40) 191 #define RCM_RCR_SOFTRST (0x80) 192 193 #define FMPLL_SYNSR_LOCK (0x00000008) 194 195 #endif /* __M5275_H__ */ 196