1 /* 2 * mcf5271.h -- Definitions for Motorola Coldfire 5271 3 * 4 * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com> 5 * Based on mcf5272sim.h of uCLinux distribution: 6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef _MCF5271_H_ 29 #define _MCF5271_H_ 30 31 #define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) 32 #define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) 33 #define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) 34 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y 35 #define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y 36 #define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y 37 38 #define MCF_FMPLL_SYNCR 0x120000 39 #define MCF_FMPLL_SYNSR 0x120004 40 41 #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) 42 #define MCF_SYNCR_MFD_4X 0x00000000 43 #define MCF_SYNCR_MFD_6X 0x01000000 44 #define MCF_SYNCR_MFD_8X 0x02000000 45 #define MCF_SYNCR_MFD_10X 0x03000000 46 #define MCF_SYNCR_MFD_12X 0x04000000 47 #define MCF_SYNCR_MFD_14X 0x05000000 48 #define MCF_SYNCR_MFD_16X 0x06000000 49 #define MCF_SYNCR_MFD_18X 0x07000000 50 51 #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) 52 #define MCF_SYNCR_RFD_DIV1 0x00000000 53 #define MCF_SYNCR_RFD_DIV2 0x00080000 54 #define MCF_SYNCR_RFD_DIV4 0x00100000 55 #define MCF_SYNCR_RFD_DIV8 0x00180000 56 #define MCF_SYNCR_RFD_DIV16 0x00200000 57 #define MCF_SYNCR_RFD_DIV32 0x00280000 58 #define MCF_SYNCR_RFD_DIV64 0x00300000 59 #define MCF_SYNCR_RFD_DIV128 0x00380000 60 61 #define MCF_FMPLL_SYNSR_LOCK 0x8 62 63 #define MCF_WTM_WCR 0x140000 64 #define MCF_WTM_WCNTR 0x140004 65 #define MCF_WTM_WSR 0x140006 66 #define MCF_WTM_WCR_EN 0x0001 67 68 #define MCF_RCM_RCR 0x110000 69 #define MCF_RCM_RCR_FRCRSTOUT 0x40 70 #define MCF_RCM_RCR_SOFTRST 0x80 71 72 #define MCF_GPIO_PODR_ADDR 0x100000 73 #define MCF_GPIO_PODR_DATAH 0x100001 74 #define MCF_GPIO_PODR_DATAL 0x100002 75 #define MCF_GPIO_PODR_BUSCTL 0x100003 76 #define MCF_GPIO_PODR_BS 0x100004 77 #define MCF_GPIO_PODR_CS 0x100005 78 #define MCF_GPIO_PODR_SDRAM 0x100006 79 #define MCF_GPIO_PODR_FECI2C 0x100007 80 #define MCF_GPIO_PODR_UARTH 0x100008 81 #define MCF_GPIO_PODR_UARTL 0x100009 82 #define MCF_GPIO_PODR_QSPI 0x10000A 83 #define MCF_GPIO_PODR_TIMER 0x10000B 84 85 #define MCF_GPIO_PDDR_ADDR 0x100010 86 #define MCF_GPIO_PDDR_DATAH 0x100011 87 #define MCF_GPIO_PDDR_DATAL 0x100012 88 #define MCF_GPIO_PDDR_BUSCTL 0x100013 89 #define MCF_GPIO_PDDR_BS 0x100014 90 #define MCF_GPIO_PDDR_CS 0x100015 91 #define MCF_GPIO_PDDR_SDRAM 0x100016 92 #define MCF_GPIO_PDDR_FECI2C 0x100017 93 #define MCF_GPIO_PDDR_UARTH 0x100018 94 #define MCF_GPIO_PDDR_UARTL 0x100019 95 #define MCF_GPIO_PDDR_QSPI 0x10001A 96 #define MCF_GPIO_PDDR_TIMER 0x10001B 97 98 #define MCF_GPIO_PPDSDR_ADDR 0x100020 99 #define MCF_GPIO_PPDSDR_DATAH 0x100021 100 #define MCF_GPIO_PPDSDR_DATAL 0x100022 101 #define MCF_GPIO_PPDSDR_BUSCTL 0x100023 102 #define MCF_GPIO_PPDSDR_BS 0x100024 103 #define MCF_GPIO_PPDSDR_CS 0x100025 104 #define MCF_GPIO_PPDSDR_SDRAM 0x100026 105 #define MCF_GPIO_PPDSDR_FECI2C 0x100027 106 #define MCF_GPIO_PPDSDR_UARTH 0x100028 107 #define MCF_GPIO_PPDSDR_UARTL 0x100029 108 #define MCF_GPIO_PPDSDR_QSPI 0x10002A 109 #define MCF_GPIO_PPDSDR_TIMER 0x10002B 110 111 #define MCF_GPIO_PCLRR_ADDR 0x100030 112 #define MCF_GPIO_PCLRR_DATAH 0x100031 113 #define MCF_GPIO_PCLRR_DATAL 0x100032 114 #define MCF_GPIO_PCLRR_BUSCTL 0x100033 115 #define MCF_GPIO_PCLRR_BS 0x100034 116 #define MCF_GPIO_PCLRR_CS 0x100035 117 #define MCF_GPIO_PCLRR_SDRAM 0x100036 118 #define MCF_GPIO_PCLRR_FECI2C 0x100037 119 #define MCF_GPIO_PCLRR_UARTH 0x100038 120 #define MCF_GPIO_PCLRR_UARTL 0x100039 121 #define MCF_GPIO_PCLRR_QSPI 0x10003A 122 #define MCF_GPIO_PCLRR_TIMER 0x10003B 123 124 #define MCF_GPIO_PAR_AD 0x100040 125 #define MCF_GPIO_PAR_BUSCTL 0x100042 126 #define MCF_GPIO_PAR_BS 0x100044 127 #define MCF_GPIO_PAR_CS 0x100045 128 #define MCF_GPIO_PAR_SDRAM 0x100046 129 #define MCF_GPIO_PAR_FECI2C 0x100047 130 #define MCF_GPIO_PAR_UART 0x100048 131 #define MCF_GPIO_PAR_QSPI 0x10004A 132 #define MCF_GPIO_PAR_TIMER 0x10004C 133 134 #define MCF_DSCR_EIM 0x100050 135 #define MCF_DCSR_FEC12C 0x100052 136 #define MCF_DCSR_UART 0x100053 137 #define MCF_DCSR_QSPI 0x100054 138 #define MCF_DCSR_TIMER 0x100055 139 140 #define MCF_CCM_CIR 0x11000A 141 #define MCF_CCM_CIR_PRN_MASK 0x3F 142 #define MCF_CCM_CIR_PIN_LEN 6 143 #define MCF_CCM_CIR_PIN_MCF5270 0x002e 144 #define MCF_CCM_CIR_PIN_MCF5271 0x0032 145 146 #define MCF_GPIO_AD_ADDR23 0x80 147 #define MCF_GPIO_AD_ADDR22 0x40 148 #define MCF_GPIO_AD_ADDR21 0x20 149 #define MCF_GPIO_AD_DATAL 0x01 150 #define MCF_GPIO_AD_MASK 0xe1 151 152 #define MCF_GPIO_PAR_CS_PAR_CS2 0x04 153 154 #define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */ 155 #define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */ 156 #define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */ 157 #define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */ 158 #define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */ 159 #define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */ 160 #define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */ 161 #define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */ 162 #define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */ 163 #define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */ 164 #define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */ 165 #define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */ 166 167 #define MCF_GPIO_PAR_UART_U0RTS 0x0001 168 #define MCF_GPIO_PAR_UART_U0CTS 0x0002 169 #define MCF_GPIO_PAR_UART_U0TXD 0x0004 170 #define MCF_GPIO_PAR_UART_U0RXD 0x0008 171 #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 172 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 173 174 #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) 175 176 #define MCF_SDRAMC_DCR 0x000040 177 #define MCF_SDRAMC_DACR0 0x000048 178 #define MCF_SDRAMC_DMR0 0x00004C 179 180 #define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) 181 #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) 182 #define MCF_SDRAMC_DCR_IS 0x0800 183 #define MCF_SDRAMC_DCR_COC 0x1000 184 #define MCF_SDRAMC_DCR_NAM 0x2000 185 186 #define MCF_SDRAMC_DACRn_IP 0x00000008 187 #define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4) 188 #define MCF_SDRAMC_DACRn_MRS 0x00000040 189 #define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8) 190 #define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12) 191 #define MCF_SDRAMC_DACRn_RE 0x00008000 192 #define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18) 193 194 #define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000 195 #define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000 196 #define MCF_SDRAMC_DMRn_V 0x00000001 197 198 #define MCFSIM_ICR1 0x000C41 199 200 /* Interrupt Controller (INTC) */ 201 #define INT0_LO_RSVD0 (0) 202 #define INT0_LO_EPORT1 (1) 203 #define INT0_LO_EPORT2 (2) 204 #define INT0_LO_EPORT3 (3) 205 #define INT0_LO_EPORT4 (4) 206 #define INT0_LO_EPORT5 (5) 207 #define INT0_LO_EPORT6 (6) 208 #define INT0_LO_EPORT7 (7) 209 #define INT0_LO_SCM (8) 210 #define INT0_LO_DMA0 (9) 211 #define INT0_LO_DMA1 (10) 212 #define INT0_LO_DMA2 (11) 213 #define INT0_LO_DMA3 (12) 214 #define INT0_LO_UART0 (13) 215 #define INT0_LO_UART1 (14) 216 #define INT0_LO_UART2 (15) 217 #define INT0_LO_RSVD1 (16) 218 #define INT0_LO_I2C (17) 219 #define INT0_LO_QSPI (18) 220 #define INT0_LO_DTMR0 (19) 221 #define INT0_LO_DTMR1 (20) 222 #define INT0_LO_DTMR2 (21) 223 #define INT0_LO_DTMR3 (22) 224 #define INT0_LO_FEC_TXF (23) 225 #define INT0_LO_FEC_TXB (24) 226 #define INT0_LO_FEC_UN (25) 227 #define INT0_LO_FEC_RL (26) 228 #define INT0_LO_FEC_RXF (27) 229 #define INT0_LO_FEC_RXB (28) 230 #define INT0_LO_FEC_MII (29) 231 #define INT0_LO_FEC_LC (30) 232 #define INT0_LO_FEC_HBERR (31) 233 #define INT0_HI_FEC_GRA (32) 234 #define INT0_HI_FEC_EBERR (33) 235 #define INT0_HI_FEC_BABT (34) 236 #define INT0_HI_FEC_BABR (35) 237 #define INT0_HI_PIT0 (36) 238 #define INT0_HI_PIT1 (37) 239 #define INT0_HI_PIT2 (38) 240 #define INT0_HI_PIT3 (39) 241 #define INT0_HI_RNG (40) 242 #define INT0_HI_SKHA (41) 243 #define INT0_HI_MDHA (42) 244 #define INT0_HI_CAN1_BUF0I (43) 245 #define INT0_HI_CAN1_BUF1I (44) 246 #define INT0_HI_CAN1_BUF2I (45) 247 #define INT0_HI_CAN1_BUF3I (46) 248 #define INT0_HI_CAN1_BUF4I (47) 249 #define INT0_HI_CAN1_BUF5I (48) 250 #define INT0_HI_CAN1_BUF6I (49) 251 #define INT0_HI_CAN1_BUF7I (50) 252 #define INT0_HI_CAN1_BUF8I (51) 253 #define INT0_HI_CAN1_BUF9I (52) 254 #define INT0_HI_CAN1_BUF10I (53) 255 #define INT0_HI_CAN1_BUF11I (54) 256 #define INT0_HI_CAN1_BUF12I (55) 257 #define INT0_HI_CAN1_BUF13I (56) 258 #define INT0_HI_CAN1_BUF14I (57) 259 #define INT0_HI_CAN1_BUF15I (58) 260 #define INT0_HI_CAN1_ERRINT (59) 261 #define INT0_HI_CAN1_BOFFINT (60) 262 /* 60-63 Reserved */ 263 264 #endif /* _MCF5271_H_ */ 265