1*819833afSPeter Tyser /* 2*819833afSPeter Tyser * mcf5271.h -- Definitions for Motorola Coldfire 5271 3*819833afSPeter Tyser * 4*819833afSPeter Tyser * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com> 5*819833afSPeter Tyser * Based on mcf5272sim.h of uCLinux distribution: 6*819833afSPeter Tyser * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 7*819833afSPeter Tyser * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8*819833afSPeter Tyser * 9*819833afSPeter Tyser * See file CREDITS for list of people who contributed to this 10*819833afSPeter Tyser * project. 11*819833afSPeter Tyser * 12*819833afSPeter Tyser * This program is free software; you can redistribute it and/or 13*819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 14*819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 15*819833afSPeter Tyser * the License, or (at your option) any later version. 16*819833afSPeter Tyser * 17*819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 18*819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 19*819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20*819833afSPeter Tyser * GNU General Public License for more details. 21*819833afSPeter Tyser * 22*819833afSPeter Tyser * You should have received a copy of the GNU General Public License 23*819833afSPeter Tyser * along with this program; if not, write to the Free Software 24*819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25*819833afSPeter Tyser * MA 02111-1307 USA 26*819833afSPeter Tyser */ 27*819833afSPeter Tyser 28*819833afSPeter Tyser #ifndef _MCF5271_H_ 29*819833afSPeter Tyser #define _MCF5271_H_ 30*819833afSPeter Tyser 31*819833afSPeter Tyser #define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) 32*819833afSPeter Tyser #define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) 33*819833afSPeter Tyser #define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) 34*819833afSPeter Tyser #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y 35*819833afSPeter Tyser #define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y 36*819833afSPeter Tyser #define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y 37*819833afSPeter Tyser 38*819833afSPeter Tyser #define MCF_FMPLL_SYNCR 0x120000 39*819833afSPeter Tyser #define MCF_FMPLL_SYNSR 0x120004 40*819833afSPeter Tyser 41*819833afSPeter Tyser #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) 42*819833afSPeter Tyser #define MCF_SYNCR_MFD_4X 0x00000000 43*819833afSPeter Tyser #define MCF_SYNCR_MFD_6X 0x01000000 44*819833afSPeter Tyser #define MCF_SYNCR_MFD_8X 0x02000000 45*819833afSPeter Tyser #define MCF_SYNCR_MFD_10X 0x03000000 46*819833afSPeter Tyser #define MCF_SYNCR_MFD_12X 0x04000000 47*819833afSPeter Tyser #define MCF_SYNCR_MFD_14X 0x05000000 48*819833afSPeter Tyser #define MCF_SYNCR_MFD_16X 0x06000000 49*819833afSPeter Tyser #define MCF_SYNCR_MFD_18X 0x07000000 50*819833afSPeter Tyser 51*819833afSPeter Tyser #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) 52*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV1 0x00000000 53*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV2 0x00080000 54*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV4 0x00100000 55*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV8 0x00180000 56*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV16 0x00200000 57*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV32 0x00280000 58*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV64 0x00300000 59*819833afSPeter Tyser #define MCF_SYNCR_RFD_DIV128 0x00380000 60*819833afSPeter Tyser 61*819833afSPeter Tyser #define MCF_FMPLL_SYNSR_LOCK 0x8 62*819833afSPeter Tyser 63*819833afSPeter Tyser #define MCF_WTM_WCR 0x140000 64*819833afSPeter Tyser #define MCF_WTM_WCNTR 0x140004 65*819833afSPeter Tyser #define MCF_WTM_WSR 0x140006 66*819833afSPeter Tyser #define MCF_WTM_WCR_EN 0x0001 67*819833afSPeter Tyser 68*819833afSPeter Tyser #define MCF_RCM_RCR 0x110000 69*819833afSPeter Tyser #define MCF_RCM_RCR_FRCRSTOUT 0x40 70*819833afSPeter Tyser #define MCF_RCM_RCR_SOFTRST 0x80 71*819833afSPeter Tyser 72*819833afSPeter Tyser #define MCF_GPIO_PODR_ADDR 0x100000 73*819833afSPeter Tyser #define MCF_GPIO_PODR_DATAH 0x100001 74*819833afSPeter Tyser #define MCF_GPIO_PODR_DATAL 0x100002 75*819833afSPeter Tyser #define MCF_GPIO_PODR_BUSCTL 0x100003 76*819833afSPeter Tyser #define MCF_GPIO_PODR_BS 0x100004 77*819833afSPeter Tyser #define MCF_GPIO_PODR_CS 0x100005 78*819833afSPeter Tyser #define MCF_GPIO_PODR_SDRAM 0x100006 79*819833afSPeter Tyser #define MCF_GPIO_PODR_FECI2C 0x100007 80*819833afSPeter Tyser #define MCF_GPIO_PODR_UARTH 0x100008 81*819833afSPeter Tyser #define MCF_GPIO_PODR_UARTL 0x100009 82*819833afSPeter Tyser #define MCF_GPIO_PODR_QSPI 0x10000A 83*819833afSPeter Tyser #define MCF_GPIO_PODR_TIMER 0x10000B 84*819833afSPeter Tyser 85*819833afSPeter Tyser #define MCF_GPIO_PDDR_ADDR 0x100010 86*819833afSPeter Tyser #define MCF_GPIO_PDDR_DATAH 0x100011 87*819833afSPeter Tyser #define MCF_GPIO_PDDR_DATAL 0x100012 88*819833afSPeter Tyser #define MCF_GPIO_PDDR_BUSCTL 0x100013 89*819833afSPeter Tyser #define MCF_GPIO_PDDR_BS 0x100014 90*819833afSPeter Tyser #define MCF_GPIO_PDDR_CS 0x100015 91*819833afSPeter Tyser #define MCF_GPIO_PDDR_SDRAM 0x100016 92*819833afSPeter Tyser #define MCF_GPIO_PDDR_FECI2C 0x100017 93*819833afSPeter Tyser #define MCF_GPIO_PDDR_UARTH 0x100018 94*819833afSPeter Tyser #define MCF_GPIO_PDDR_UARTL 0x100019 95*819833afSPeter Tyser #define MCF_GPIO_PDDR_QSPI 0x10001A 96*819833afSPeter Tyser #define MCF_GPIO_PDDR_TIMER 0x10001B 97*819833afSPeter Tyser 98*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_ADDR 0x100020 99*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_DATAH 0x100021 100*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_DATAL 0x100022 101*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_BUSCTL 0x100023 102*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_BS 0x100024 103*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_CS 0x100025 104*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_SDRAM 0x100026 105*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_FECI2C 0x100027 106*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_UARTH 0x100028 107*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_UARTL 0x100029 108*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_QSPI 0x10002A 109*819833afSPeter Tyser #define MCF_GPIO_PPDSDR_TIMER 0x10002B 110*819833afSPeter Tyser 111*819833afSPeter Tyser #define MCF_GPIO_PCLRR_ADDR 0x100030 112*819833afSPeter Tyser #define MCF_GPIO_PCLRR_DATAH 0x100031 113*819833afSPeter Tyser #define MCF_GPIO_PCLRR_DATAL 0x100032 114*819833afSPeter Tyser #define MCF_GPIO_PCLRR_BUSCTL 0x100033 115*819833afSPeter Tyser #define MCF_GPIO_PCLRR_BS 0x100034 116*819833afSPeter Tyser #define MCF_GPIO_PCLRR_CS 0x100035 117*819833afSPeter Tyser #define MCF_GPIO_PCLRR_SDRAM 0x100036 118*819833afSPeter Tyser #define MCF_GPIO_PCLRR_FECI2C 0x100037 119*819833afSPeter Tyser #define MCF_GPIO_PCLRR_UARTH 0x100038 120*819833afSPeter Tyser #define MCF_GPIO_PCLRR_UARTL 0x100039 121*819833afSPeter Tyser #define MCF_GPIO_PCLRR_QSPI 0x10003A 122*819833afSPeter Tyser #define MCF_GPIO_PCLRR_TIMER 0x10003B 123*819833afSPeter Tyser 124*819833afSPeter Tyser #define MCF_GPIO_PAR_AD 0x100040 125*819833afSPeter Tyser #define MCF_GPIO_PAR_BUSCTL 0x100042 126*819833afSPeter Tyser #define MCF_GPIO_PAR_BS 0x100044 127*819833afSPeter Tyser #define MCF_GPIO_PAR_CS 0x100045 128*819833afSPeter Tyser #define MCF_GPIO_PAR_SDRAM 0x100046 129*819833afSPeter Tyser #define MCF_GPIO_PAR_FECI2C 0x100047 130*819833afSPeter Tyser #define MCF_GPIO_PAR_UART 0x100048 131*819833afSPeter Tyser #define MCF_GPIO_PAR_QSPI 0x10004A 132*819833afSPeter Tyser #define MCF_GPIO_PAR_TIMER 0x10004C 133*819833afSPeter Tyser 134*819833afSPeter Tyser #define MCF_DSCR_EIM 0x100050 135*819833afSPeter Tyser #define MCF_DCSR_FEC12C 0x100052 136*819833afSPeter Tyser #define MCF_DCSR_UART 0x100053 137*819833afSPeter Tyser #define MCF_DCSR_QSPI 0x100054 138*819833afSPeter Tyser #define MCF_DCSR_TIMER 0x100055 139*819833afSPeter Tyser 140*819833afSPeter Tyser #define MCF_CCM_CIR 0x11000A 141*819833afSPeter Tyser #define MCF_CCM_CIR_PRN_MASK 0x3F 142*819833afSPeter Tyser #define MCF_CCM_CIR_PIN_LEN 6 143*819833afSPeter Tyser #define MCF_CCM_CIR_PIN_MCF5270 0x002e 144*819833afSPeter Tyser #define MCF_CCM_CIR_PIN_MCF5271 0x0032 145*819833afSPeter Tyser 146*819833afSPeter Tyser #define MCF_GPIO_AD_ADDR23 0x80 147*819833afSPeter Tyser #define MCF_GPIO_AD_ADDR22 0x40 148*819833afSPeter Tyser #define MCF_GPIO_AD_ADDR21 0x20 149*819833afSPeter Tyser #define MCF_GPIO_AD_DATAL 0x01 150*819833afSPeter Tyser #define MCF_GPIO_AD_MASK 0xe1 151*819833afSPeter Tyser 152*819833afSPeter Tyser #define MCF_GPIO_PAR_CS_PAR_CS2 0x04 153*819833afSPeter Tyser 154*819833afSPeter Tyser #define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */ 155*819833afSPeter Tyser #define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */ 156*819833afSPeter Tyser #define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */ 157*819833afSPeter Tyser #define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */ 158*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */ 159*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */ 160*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */ 161*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */ 162*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */ 163*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */ 164*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */ 165*819833afSPeter Tyser #define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */ 166*819833afSPeter Tyser 167*819833afSPeter Tyser #define MCF_GPIO_PAR_UART_U0RTS 0x0001 168*819833afSPeter Tyser #define MCF_GPIO_PAR_UART_U0CTS 0x0002 169*819833afSPeter Tyser #define MCF_GPIO_PAR_UART_U0TXD 0x0004 170*819833afSPeter Tyser #define MCF_GPIO_PAR_UART_U0RXD 0x0008 171*819833afSPeter Tyser #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 172*819833afSPeter Tyser #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 173*819833afSPeter Tyser 174*819833afSPeter Tyser #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) 175*819833afSPeter Tyser 176*819833afSPeter Tyser #define MCF_SDRAMC_DCR 0x000040 177*819833afSPeter Tyser #define MCF_SDRAMC_DACR0 0x000048 178*819833afSPeter Tyser #define MCF_SDRAMC_DMR0 0x00004C 179*819833afSPeter Tyser 180*819833afSPeter Tyser #define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) 181*819833afSPeter Tyser #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) 182*819833afSPeter Tyser #define MCF_SDRAMC_DCR_IS 0x0800 183*819833afSPeter Tyser #define MCF_SDRAMC_DCR_COC 0x1000 184*819833afSPeter Tyser #define MCF_SDRAMC_DCR_NAM 0x2000 185*819833afSPeter Tyser 186*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_IP 0x00000008 187*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4) 188*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_MRS 0x00000040 189*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8) 190*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12) 191*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_RE 0x00008000 192*819833afSPeter Tyser #define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18) 193*819833afSPeter Tyser 194*819833afSPeter Tyser #define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000 195*819833afSPeter Tyser #define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000 196*819833afSPeter Tyser #define MCF_SDRAMC_DMRn_V 0x00000001 197*819833afSPeter Tyser 198*819833afSPeter Tyser #define MCFSIM_ICR1 0x000C41 199*819833afSPeter Tyser 200*819833afSPeter Tyser /* Interrupt Controller (INTC) */ 201*819833afSPeter Tyser #define INT0_LO_RSVD0 (0) 202*819833afSPeter Tyser #define INT0_LO_EPORT1 (1) 203*819833afSPeter Tyser #define INT0_LO_EPORT2 (2) 204*819833afSPeter Tyser #define INT0_LO_EPORT3 (3) 205*819833afSPeter Tyser #define INT0_LO_EPORT4 (4) 206*819833afSPeter Tyser #define INT0_LO_EPORT5 (5) 207*819833afSPeter Tyser #define INT0_LO_EPORT6 (6) 208*819833afSPeter Tyser #define INT0_LO_EPORT7 (7) 209*819833afSPeter Tyser #define INT0_LO_SCM (8) 210*819833afSPeter Tyser #define INT0_LO_DMA0 (9) 211*819833afSPeter Tyser #define INT0_LO_DMA1 (10) 212*819833afSPeter Tyser #define INT0_LO_DMA2 (11) 213*819833afSPeter Tyser #define INT0_LO_DMA3 (12) 214*819833afSPeter Tyser #define INT0_LO_UART0 (13) 215*819833afSPeter Tyser #define INT0_LO_UART1 (14) 216*819833afSPeter Tyser #define INT0_LO_UART2 (15) 217*819833afSPeter Tyser #define INT0_LO_RSVD1 (16) 218*819833afSPeter Tyser #define INT0_LO_I2C (17) 219*819833afSPeter Tyser #define INT0_LO_QSPI (18) 220*819833afSPeter Tyser #define INT0_LO_DTMR0 (19) 221*819833afSPeter Tyser #define INT0_LO_DTMR1 (20) 222*819833afSPeter Tyser #define INT0_LO_DTMR2 (21) 223*819833afSPeter Tyser #define INT0_LO_DTMR3 (22) 224*819833afSPeter Tyser #define INT0_LO_FEC_TXF (23) 225*819833afSPeter Tyser #define INT0_LO_FEC_TXB (24) 226*819833afSPeter Tyser #define INT0_LO_FEC_UN (25) 227*819833afSPeter Tyser #define INT0_LO_FEC_RL (26) 228*819833afSPeter Tyser #define INT0_LO_FEC_RXF (27) 229*819833afSPeter Tyser #define INT0_LO_FEC_RXB (28) 230*819833afSPeter Tyser #define INT0_LO_FEC_MII (29) 231*819833afSPeter Tyser #define INT0_LO_FEC_LC (30) 232*819833afSPeter Tyser #define INT0_LO_FEC_HBERR (31) 233*819833afSPeter Tyser #define INT0_HI_FEC_GRA (32) 234*819833afSPeter Tyser #define INT0_HI_FEC_EBERR (33) 235*819833afSPeter Tyser #define INT0_HI_FEC_BABT (34) 236*819833afSPeter Tyser #define INT0_HI_FEC_BABR (35) 237*819833afSPeter Tyser #define INT0_HI_PIT0 (36) 238*819833afSPeter Tyser #define INT0_HI_PIT1 (37) 239*819833afSPeter Tyser #define INT0_HI_PIT2 (38) 240*819833afSPeter Tyser #define INT0_HI_PIT3 (39) 241*819833afSPeter Tyser #define INT0_HI_RNG (40) 242*819833afSPeter Tyser #define INT0_HI_SKHA (41) 243*819833afSPeter Tyser #define INT0_HI_MDHA (42) 244*819833afSPeter Tyser #define INT0_HI_CAN1_BUF0I (43) 245*819833afSPeter Tyser #define INT0_HI_CAN1_BUF1I (44) 246*819833afSPeter Tyser #define INT0_HI_CAN1_BUF2I (45) 247*819833afSPeter Tyser #define INT0_HI_CAN1_BUF3I (46) 248*819833afSPeter Tyser #define INT0_HI_CAN1_BUF4I (47) 249*819833afSPeter Tyser #define INT0_HI_CAN1_BUF5I (48) 250*819833afSPeter Tyser #define INT0_HI_CAN1_BUF6I (49) 251*819833afSPeter Tyser #define INT0_HI_CAN1_BUF7I (50) 252*819833afSPeter Tyser #define INT0_HI_CAN1_BUF8I (51) 253*819833afSPeter Tyser #define INT0_HI_CAN1_BUF9I (52) 254*819833afSPeter Tyser #define INT0_HI_CAN1_BUF10I (53) 255*819833afSPeter Tyser #define INT0_HI_CAN1_BUF11I (54) 256*819833afSPeter Tyser #define INT0_HI_CAN1_BUF12I (55) 257*819833afSPeter Tyser #define INT0_HI_CAN1_BUF13I (56) 258*819833afSPeter Tyser #define INT0_HI_CAN1_BUF14I (57) 259*819833afSPeter Tyser #define INT0_HI_CAN1_BUF15I (58) 260*819833afSPeter Tyser #define INT0_HI_CAN1_ERRINT (59) 261*819833afSPeter Tyser #define INT0_HI_CAN1_BOFFINT (60) 262*819833afSPeter Tyser /* 60-63 Reserved */ 263*819833afSPeter Tyser 264*819833afSPeter Tyser #endif /* _MCF5271_H_ */ 265