1*819833afSPeter Tyser /* 2*819833afSPeter Tyser * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3*819833afSPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 4*819833afSPeter Tyser * 5*819833afSPeter Tyser * See file CREDITS for list of people who contributed to this 6*819833afSPeter Tyser * project. 7*819833afSPeter Tyser * 8*819833afSPeter Tyser * This program is free software; you can redistribute it and/or 9*819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 10*819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 11*819833afSPeter Tyser * the License, or (at your option) any later version. 12*819833afSPeter Tyser * 13*819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 14*819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*819833afSPeter Tyser * GNU General Public License for more details. 17*819833afSPeter Tyser * 18*819833afSPeter Tyser * You should have received a copy of the GNU General Public License 19*819833afSPeter Tyser * along with this program; if not, write to the Free Software 20*819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*819833afSPeter Tyser * MA 02111-1307 USA 22*819833afSPeter Tyser */ 23*819833afSPeter Tyser 24*819833afSPeter Tyser #ifndef m5253_h 25*819833afSPeter Tyser #define m5253_h 26*819833afSPeter Tyser /****************************************************************************/ 27*819833afSPeter Tyser 28*819833afSPeter Tyser /* 29*819833afSPeter Tyser * PLL Module (PLL) 30*819833afSPeter Tyser */ 31*819833afSPeter Tyser 32*819833afSPeter Tyser /* Register read/write macros */ 33*819833afSPeter Tyser #define PLL_PLLCR (0x000180) 34*819833afSPeter Tyser 35*819833afSPeter Tyser #define SIM_RSR (0x000000) 36*819833afSPeter Tyser #define SIM_SYPCR (0x000001) 37*819833afSPeter Tyser #define SIM_SWIVR (0x000002) 38*819833afSPeter Tyser #define SIM_SWSR (0x000003) 39*819833afSPeter Tyser #define SIM_MPARK (0x00000C) 40*819833afSPeter Tyser 41*819833afSPeter Tyser /* Bit definitions and macros for RSR */ 42*819833afSPeter Tyser #define SIM_RSR_SWTR (0x20) 43*819833afSPeter Tyser #define SIM_RSR_HRST (0x80) 44*819833afSPeter Tyser 45*819833afSPeter Tyser /* Register read/write macros */ 46*819833afSPeter Tyser #define CIM_MISCCR (0x000500) 47*819833afSPeter Tyser #define CIM_ATA_DADDR (0x000504) 48*819833afSPeter Tyser #define CIM_ATA_DCOUNT (0x000508) 49*819833afSPeter Tyser #define CIM_RTC_TIME (0x00050C) 50*819833afSPeter Tyser #define CIM_USB_CANCLK (0x000510) 51*819833afSPeter Tyser 52*819833afSPeter Tyser /* Bit definitions and macros for MISCCR */ 53*819833afSPeter Tyser #define CIM_MISCCR_ADTA (0x00000001) 54*819833afSPeter Tyser #define CIM_MISCCR_ADTD (0x00000002) 55*819833afSPeter Tyser #define CIM_MISCCR_ADIE (0x00000004) 56*819833afSPeter Tyser #define CIM_MISCCR_ADIC (0x00000008) 57*819833afSPeter Tyser #define CIM_MISCCR_ADIP (0x00000010) 58*819833afSPeter Tyser #define CIM_MISCCR_CPUEND (0x00000020) 59*819833afSPeter Tyser #define CIM_MISCCR_DMAEND (0x00000040) 60*819833afSPeter Tyser #define CIM_MISCCR_RTCCLR (0x00000080) 61*819833afSPeter Tyser #define CIM_MISCCR_RTCPL (0x00000100) 62*819833afSPeter Tyser #define CIM_MISCCR_URIE (0x00000800) 63*819833afSPeter Tyser #define CIM_MISCCR_URIC (0x00001000) 64*819833afSPeter Tyser #define CIM_MISCCR_URIP (0x00002000) 65*819833afSPeter Tyser 66*819833afSPeter Tyser /* Bit definitions and macros for ATA_DADDR */ 67*819833afSPeter Tyser #define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2) 68*819833afSPeter Tyser #define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18) 69*819833afSPeter Tyser 70*819833afSPeter Tyser /* Bit definitions and macros for ATA_DCOUNT */ 71*819833afSPeter Tyser #define CIM_ATA_DCOUNT_COUNT(x) (((x)&0x0000FFFF)) 72*819833afSPeter Tyser 73*819833afSPeter Tyser #endif /* m5253_h */ 74