1 /* 2 * MCF5445x Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __IMMAP_5445X__ 11 #define __IMMAP_5445X__ 12 13 /* Module Base Addresses */ 14 #define MMAP_SCM1 0xFC000000 15 #define MMAP_XBS 0xFC004000 16 #define MMAP_FBCS 0xFC008000 17 #define MMAP_FEC0 0xFC030000 18 #define MMAP_FEC1 0xFC034000 19 #define MMAP_RTC 0xFC03C000 20 #define MMAP_SCM2 0xFC040000 21 #define MMAP_EDMA 0xFC044000 22 #define MMAP_INTC0 0xFC048000 23 #define MMAP_INTC1 0xFC04C000 24 #define MMAP_IACK 0xFC054000 25 #define MMAP_I2C 0xFC058000 26 #define MMAP_DSPI 0xFC05C000 27 #define MMAP_UART0 0xFC060000 28 #define MMAP_UART1 0xFC064000 29 #define MMAP_UART2 0xFC068000 30 #define MMAP_DTMR0 0xFC070000 31 #define MMAP_DTMR1 0xFC074000 32 #define MMAP_DTMR2 0xFC078000 33 #define MMAP_DTMR3 0xFC07C000 34 #define MMAP_PIT0 0xFC080000 35 #define MMAP_PIT1 0xFC084000 36 #define MMAP_PIT2 0xFC088000 37 #define MMAP_PIT3 0xFC08C000 38 #define MMAP_EPORT 0xFC094000 39 #define MMAP_WTM 0xFC098000 40 #define MMAP_SBF 0xFC0A0000 41 #define MMAP_RCM 0xFC0A0000 42 #define MMAP_CCM 0xFC0A0000 43 #define MMAP_GPIO 0xFC0A4000 44 #define MMAP_PCI 0xFC0A8000 45 #define MMAP_PCIARB 0xFC0AC000 46 #define MMAP_RNG 0xFC0B4000 47 #define MMAP_SDRAM 0xFC0B8000 48 #define MMAP_SSI 0xFC0BC000 49 #define MMAP_PLL 0xFC0C4000 50 #define MMAP_ATA 0x90000000 51 #define MMAP_USBHW 0xFC0B0000 52 #define MMAP_USBCAPS 0xFC0B0100 53 #define MMAP_USBEHCI 0xFC0B0140 54 #define MMAP_USBOTG 0xFC0B01A0 55 56 #include <asm/coldfire/ata.h> 57 #include <asm/coldfire/crossbar.h> 58 #include <asm/coldfire/dspi.h> 59 #include <asm/coldfire/edma.h> 60 #include <asm/coldfire/eport.h> 61 #include <asm/coldfire/flexbus.h> 62 #include <asm/coldfire/intctrl.h> 63 #include <asm/coldfire/ssi.h> 64 65 /* Watchdog Timer Modules (WTM) */ 66 typedef struct wtm { 67 u16 wcr; 68 u16 wmr; 69 u16 wcntr; 70 u16 wsr; 71 } wtm_t; 72 73 /* Serial Boot Facility (SBF) */ 74 typedef struct sbf { 75 u8 resv0[0x18]; 76 u16 sbfsr; /* Serial Boot Facility Status Register */ 77 u8 resv1[0x6]; 78 u16 sbfcr; /* Serial Boot Facility Control Register */ 79 } sbf_t; 80 81 /* Reset Controller Module (RCM) */ 82 typedef struct rcm { 83 u8 rcr; 84 u8 rsr; 85 } rcm_t; 86 87 /* Chip Configuration Module (CCM) */ 88 typedef struct ccm { 89 u8 ccm_resv0[0x4]; 90 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ 91 u8 resv1[0x2]; 92 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ 93 u16 cir; /* Chip Identification Register (Read-only) */ 94 u8 resv2[0x4]; 95 u16 misccr; /* Miscellaneous Control Register */ 96 u16 cdr; /* Clock Divider Register */ 97 u16 uocsr; /* USB On-the-Go Controller Status Register */ 98 } ccm_t; 99 100 /* General Purpose I/O Module (GPIO) */ 101 typedef struct gpio { 102 u8 podr_fec0h; /* FEC0 High Port Output Data Register */ 103 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ 104 u8 podr_ssi; /* SSI Port Output Data Register */ 105 u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ 106 u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ 107 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ 108 u8 podr_dma; /* DMA Port Output Data Register */ 109 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ 110 u8 resv0[0x1]; 111 u8 podr_uart; /* UART Port Output Data Register */ 112 u8 podr_dspi; /* DSPI Port Output Data Register */ 113 u8 podr_timer; /* Timer Port Output Data Register */ 114 u8 podr_pci; /* PCI Port Output Data Register */ 115 u8 podr_usb; /* USB Port Output Data Register */ 116 u8 podr_atah; /* ATA High Port Output Data Register */ 117 u8 podr_atal; /* ATA Low Port Output Data Register */ 118 u8 podr_fec1h; /* FEC1 High Port Output Data Register */ 119 u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ 120 u8 resv1[0x2]; 121 u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ 122 u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ 123 u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ 124 u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ 125 u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ 126 u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ 127 u8 pddr_ssi; /* SSI Port Data Direction Register */ 128 u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ 129 u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ 130 u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ 131 u8 pddr_dma; /* DMA Port Data Direction Register */ 132 u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ 133 u8 resv2[0x1]; 134 u8 pddr_uart; /* UART Port Data Direction Register */ 135 u8 pddr_dspi; /* DSPI Port Data Direction Register */ 136 u8 pddr_timer; /* Timer Port Data Direction Register */ 137 u8 pddr_pci; /* PCI Port Data Direction Register */ 138 u8 pddr_usb; /* USB Port Data Direction Register */ 139 u8 pddr_atah; /* ATA High Port Data Direction Register */ 140 u8 pddr_atal; /* ATA Low Port Data Direction Register */ 141 u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ 142 u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ 143 u8 resv3[0x2]; 144 u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ 145 u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ 146 u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ 147 u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ 148 u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ 149 u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ 150 u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ 151 u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ 152 u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ 153 u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ 154 u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ 155 u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ 156 u8 resv4[0x1]; 157 u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ 158 u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ 159 u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ 160 u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ 161 u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ 162 u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ 163 u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ 164 u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ 165 u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ 166 u8 resv5[0x2]; 167 u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ 168 u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ 169 u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ 170 u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ 171 u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ 172 u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ 173 u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ 174 u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ 175 u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ 176 u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ 177 u8 pclrr_dma; /* DMA Port Clear Output Data Register */ 178 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ 179 u8 resv6[0x1]; 180 u8 pclrr_uart; /* UART Port Clear Output Data Register */ 181 u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ 182 u8 pclrr_timer; /* Timer Port Clear Output Data Register */ 183 u8 pclrr_pci; /* PCI Port Clear Output Data Register */ 184 u8 pclrr_usb; /* USB Port Clear Output Data Register */ 185 u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ 186 u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ 187 u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ 188 u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ 189 u8 resv7[0x2]; 190 u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ 191 u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ 192 u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ 193 u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ 194 u8 par_fec; /* FEC Pin Assignment Register */ 195 u8 par_dma; /* DMA Pin Assignment Register */ 196 u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ 197 u8 par_dspi; /* DSPI Pin Assignment Register */ 198 u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ 199 u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ 200 u8 par_timer; /* Time Pin Assignment Register */ 201 u8 par_usb; /* USB Pin Assignment Register */ 202 u8 resv8[0x1]; 203 u8 par_uart; /* UART Pin Assignment Register */ 204 u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ 205 u16 par_ssi; /* SSI Pin Assignment Register */ 206 u16 par_ata; /* ATA Pin Assignment Register */ 207 u8 par_irq; /* IRQ Pin Assignment Register */ 208 u8 resv9[0x1]; 209 u16 par_pci; /* PCI Pin Assignment Register */ 210 u8 mscr_sdram; /* SDRAM Mode Select Control Register */ 211 u8 mscr_pci; /* PCI Mode Select Control Register */ 212 u8 resv10[0x2]; 213 u8 dscr_i2c; /* I2C Drive Strength Control Register */ 214 u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ 215 u8 dscr_fec; /* FEC Drive Strength Control Register */ 216 u8 dscr_uart; /* UART Drive Strength Control Register */ 217 u8 dscr_dspi; /* DSPI Drive Strength Control Register */ 218 u8 dscr_timer; /* TIMER Drive Strength Control Register */ 219 u8 dscr_ssi; /* SSI Drive Strength Control Register */ 220 u8 dscr_dma; /* DMA Drive Strength Control Register */ 221 u8 dscr_debug; /* DEBUG Drive Strength Control Register */ 222 u8 dscr_reset; /* RESET Drive Strength Control Register */ 223 u8 dscr_irq; /* IRQ Drive Strength Control Register */ 224 u8 dscr_usb; /* USB Drive Strength Control Register */ 225 u8 dscr_ata; /* ATA Drive Strength Control Register */ 226 } gpio_t; 227 228 /* SDRAM Controller (SDRAMC) */ 229 typedef struct sdramc { 230 u32 sdmr; /* SDRAM Mode/Extended Mode Register */ 231 u32 sdcr; /* SDRAM Control Register */ 232 u32 sdcfg1; /* SDRAM Configuration Register 1 */ 233 u32 sdcfg2; /* SDRAM Chip Select Register */ 234 u8 resv0[0x100]; 235 u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ 236 u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ 237 } sdramc_t; 238 239 /* Phase Locked Loop (PLL) */ 240 typedef struct pll { 241 u32 pcr; /* PLL Control Register */ 242 u32 psr; /* PLL Status Register */ 243 } pll_t; 244 245 typedef struct pci { 246 u32 idr; /* 0x00 Device Id / Vendor Id Register */ 247 u32 scr; /* 0x04 Status / command Register */ 248 u32 ccrir; /* 0x08 Class Code / Revision Id Register */ 249 u32 cr1; /* 0x0c Configuration 1 Register */ 250 u32 bar0; /* 0x10 Base address register 0 Register */ 251 u32 bar1; /* 0x14 Base address register 1 Register */ 252 u32 bar2; /* 0x18 Base address register 2 Register */ 253 u32 bar3; /* 0x1c Base address register 3 Register */ 254 u32 bar4; /* 0x20 Base address register 4 Register */ 255 u32 bar5; /* 0x24 Base address register 5 Register */ 256 u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ 257 u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ 258 u32 erbar; /* 0x30 Expansion ROM Base Address Register */ 259 u32 cpr; /* 0x34 Capabilities Pointer Register */ 260 u32 rsvd1; /* 0x38 */ 261 u32 cr2; /* 0x3c Configuration Register 2 */ 262 u32 rsvd2[8]; /* 0x40 - 0x5f */ 263 264 /* General control / status registers */ 265 u32 gscr; /* 0x60 Global Status / Control Register */ 266 u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ 267 u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ 268 u32 tcr1; /* 0x6c Target Control 1 Register */ 269 u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ 270 u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ 271 u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ 272 u32 rsvd3; /* 0x7c */ 273 u32 iwcr; /* 0x80 Initiator Window Configuration Register */ 274 u32 icr; /* 0x84 Initiator Control Register */ 275 u32 isr; /* 0x88 Initiator Status Register */ 276 u32 tcr2; /* 0x8c Target Control 2 Register */ 277 u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ 278 u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ 279 u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ 280 u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ 281 u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ 282 u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ 283 u32 intr; /* 0xa8 Interrupt Register */ 284 u32 rsvd4[19]; /* 0xac - 0xf7 */ 285 u32 car; /* 0xf8 Configuration Address Register */ 286 } pci_t; 287 288 typedef struct pci_arbiter { 289 /* Pci Arbiter Registers */ 290 union { 291 u32 acr; /* Arbiter Control Register */ 292 u32 asr; /* Arbiter Status Register */ 293 }; 294 } pciarb_t; 295 296 /* Register read/write struct */ 297 typedef struct scm1 { 298 u32 mpr; /* 0x00 Master Privilege Register */ 299 u32 rsvd1[7]; 300 u32 pacra; /* 0x20 Peripheral Access Control Register A */ 301 u32 pacrb; /* 0x24 Peripheral Access Control Register B */ 302 u32 pacrc; /* 0x28 Peripheral Access Control Register C */ 303 u32 pacrd; /* 0x2C Peripheral Access Control Register D */ 304 u32 rsvd2[4]; 305 u32 pacre; /* 0x40 Peripheral Access Control Register E */ 306 u32 pacrf; /* 0x44 Peripheral Access Control Register F */ 307 u32 pacrg; /* 0x48 Peripheral Access Control Register G */ 308 } scm1_t; 309 310 typedef struct scm2 { 311 u8 rsvd1[19]; /* 0x00 - 0x12 */ 312 u8 wcr; /* 0x13 */ 313 u16 rsvd2; /* 0x14 - 0x15 */ 314 u16 cwcr; /* 0x16 */ 315 u8 rsvd3[3]; /* 0x18 - 0x1A */ 316 u8 cwsr; /* 0x1B */ 317 u8 rsvd4[3]; /* 0x1C - 0x1E */ 318 u8 scmisr; /* 0x1F */ 319 u32 rsvd5; /* 0x20 - 0x23 */ 320 u8 bcr; /* 0x24 */ 321 u8 rsvd6[74]; /* 0x25 - 0x6F */ 322 u32 cfadr; /* 0x70 */ 323 u8 rsvd7; /* 0x74 */ 324 u8 cfier; /* 0x75 */ 325 u8 cfloc; /* 0x76 */ 326 u8 cfatr; /* 0x77 */ 327 u32 rsvd8; /* 0x78 - 0x7B */ 328 u32 cfdtr; /* 0x7C */ 329 } scm2_t; 330 331 typedef struct rtcex { 332 u32 rsvd1[3]; 333 u32 gocu; 334 u32 gocl; 335 } rtcex_t; 336 #endif /* __IMMAP_5445X__ */ 337