1 /* 2 * MCF5329 Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __IMMAP_5329__ 27 #define __IMMAP_5329__ 28 29 #define MMAP_SCM1 0xEC000000 30 #define MMAP_MDHA 0xEC080000 31 #define MMAP_SKHA 0xEC084000 32 #define MMAP_RNG 0xEC088000 33 #define MMAP_SCM2 0xFC000000 34 #define MMAP_XBS 0xFC004000 35 #define MMAP_FBCS 0xFC008000 36 #define MMAP_CAN 0xFC020000 37 #define MMAP_FEC 0xFC030000 38 #define MMAP_SCM3 0xFC040000 39 #define MMAP_EDMA 0xFC044000 40 #define MMAP_TCD 0xFC045000 41 #define MMAP_INTC0 0xFC048000 42 #define MMAP_INTC1 0xFC04C000 43 #define MMAP_INTCACK 0xFC054000 44 #define MMAP_I2C 0xFC058000 45 #define MMAP_QSPI 0xFC05C000 46 #define MMAP_UART0 0xFC060000 47 #define MMAP_UART1 0xFC064000 48 #define MMAP_UART2 0xFC068000 49 #define MMAP_DTMR0 0xFC070000 50 #define MMAP_DTMR1 0xFC074000 51 #define MMAP_DTMR2 0xFC078000 52 #define MMAP_DTMR3 0xFC07C000 53 #define MMAP_PIT0 0xFC080000 54 #define MMAP_PIT1 0xFC084000 55 #define MMAP_PIT2 0xFC088000 56 #define MMAP_PIT3 0xFC08C000 57 #define MMAP_PWM 0xFC090000 58 #define MMAP_EPORT 0xFC094000 59 #define MMAP_WDOG 0xFC098000 60 #define MMAP_RCM 0xFC0A0000 61 #define MMAP_CCM 0xFC0A0004 62 #define MMAP_GPIO 0xFC0A4000 63 #define MMAP_RTC 0xFC0A8000 64 #define MMAP_LCDC 0xFC0AC000 65 #define MMAP_USBOTG 0xFC0B0000 66 #define MMAP_USBH 0xFC0B4000 67 #define MMAP_SDRAM 0xFC0B8000 68 #define MMAP_SSI 0xFC0BC000 69 #define MMAP_PLL 0xFC0C0000 70 71 #include <asm/coldfire/crossbar.h> 72 #include <asm/coldfire/edma.h> 73 #include <asm/coldfire/eport.h> 74 #include <asm/coldfire/qspi.h> 75 #include <asm/coldfire/flexbus.h> 76 #include <asm/coldfire/flexcan.h> 77 #include <asm/coldfire/intctrl.h> 78 #include <asm/coldfire/lcd.h> 79 #include <asm/coldfire/mdha.h> 80 #include <asm/coldfire/pwm.h> 81 #include <asm/coldfire/ssi.h> 82 #include <asm/coldfire/skha.h> 83 84 /* System control module registers */ 85 typedef struct scm1_ctrl { 86 u32 mpr0; /* 0x00 Master Privilege Register 0 */ 87 u32 res1[15]; /* 0x04 - 0x3F */ 88 u32 pacrh; /* 0x40 Peripheral Access Control Register H */ 89 u32 res2[3]; /* 0x44 - 0x53 */ 90 u32 bmt0; /*0x54 Bus Monitor Timeout 0 */ 91 } scm1_t; 92 93 /* System control module registers 2 */ 94 typedef struct scm2_ctrl { 95 u32 mpr1; /* 0x00 Master Privilege Register */ 96 u32 res1[7]; /* 0x04 - 0x1F */ 97 u32 pacra; /* 0x20 Peripheral Access Control Register A */ 98 u32 pacrb; /* 0x24 Peripheral Access Control Register B */ 99 u32 pacrc; /* 0x28 Peripheral Access Control Register C */ 100 u32 pacrd; /* 0x2C Peripheral Access Control Register D */ 101 u32 res2[4]; /* 0x30 - 0x3F */ 102 u32 pacre; /* 0x40 Peripheral Access Control Register E */ 103 u32 pacrf; /* 0x44 Peripheral Access Control Register F */ 104 u32 pacrg; /* 0x48 Peripheral Access Control Register G */ 105 u32 res3[2]; /* 0x4C - 0x53 */ 106 u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */ 107 } scm2_t; 108 109 /* System Control Module register 3 */ 110 typedef struct scm3_ctrl { 111 u8 res1[19]; /* 0x00 - 0x12 */ 112 u8 wcr; /* 0x13 wakeup control register */ 113 u16 res2; /* 0x14 - 0x15 */ 114 u16 cwcr; /* 0x16 Core Watchdog Control Register */ 115 u8 res3[3]; /* 0x18 - 0x1A */ 116 u8 cwsr; /* 0x1B Core Watchdog Service Register */ 117 u8 res4[2]; /* 0x1C - 0x1D */ 118 u8 scmisr; /* 0x1F Interrupt Status Register */ 119 u32 res5; /* 0x20 */ 120 u32 bcr; /* 0x24 Burst Configuration Register */ 121 u32 res6[18]; /* 0x28 - 0x6F */ 122 u32 cfadr; /* 0x70 Core Fault Address Register */ 123 u8 res7[4]; /* 0x71 - 0x74 */ 124 u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */ 125 u8 cfloc; /* 0x76 Core Fault Location Register */ 126 u8 cfatr; /* 0x77 Core Fault Attributes Register */ 127 u32 res8; /* 0x78 */ 128 u32 cfdtr; /* 0x7C Core Fault Data Register */ 129 } scm3_t; 130 131 typedef struct canex_ctrl { 132 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 133 } canex_t; 134 135 /* Watchdog registers */ 136 typedef struct wdog_ctrl { 137 u16 cr; /* 0x00 Control register */ 138 u16 mr; /* 0x02 Modulus register */ 139 u16 cntr; /* 0x04 Count register */ 140 u16 sr; /* 0x06 Service register */ 141 } wdog_t; 142 143 /*Chip configuration module registers */ 144 typedef struct ccm_ctrl { 145 u16 ccr; /* 0x00 Chip configuration register */ 146 u16 res2; /* 0x02 */ 147 u16 rcon; /* 0x04 Rreset configuration register */ 148 u16 cir; /* 0x06 Chip identification register */ 149 u32 res3; /* 0x08 */ 150 u16 misccr; /* 0x0A Miscellaneous control register */ 151 u16 cdr; /* 0x0C Clock divider register */ 152 u16 uhcsr; /* 0x10 USB Host controller status register */ 153 u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */ 154 } ccm_t; 155 156 typedef struct rcm { 157 u8 rcr; 158 u8 rsr; 159 } rcm_t; 160 161 /* GPIO port registers */ 162 typedef struct gpio_ctrl { 163 /* Port Output Data Registers */ 164 #ifdef CONFIG_M5329 165 u8 podr_fech; /* 0x00 */ 166 u8 podr_fecl; /* 0x01 */ 167 #else 168 u16 res00; /* 0x00 - 0x01 */ 169 #endif 170 u8 podr_ssi; /* 0x02 */ 171 u8 podr_busctl; /* 0x03 */ 172 u8 podr_be; /* 0x04 */ 173 u8 podr_cs; /* 0x05 */ 174 u8 podr_pwm; /* 0x06 */ 175 u8 podr_feci2c; /* 0x07 */ 176 u8 res08; /* 0x08 */ 177 u8 podr_uart; /* 0x09 */ 178 u8 podr_qspi; /* 0x0A */ 179 u8 podr_timer; /* 0x0B */ 180 #ifdef CONFIG_M5329 181 u8 res0C; /* 0x0C */ 182 u8 podr_lcddatah; /* 0x0D */ 183 u8 podr_lcddatam; /* 0x0E */ 184 u8 podr_lcddatal; /* 0x0F */ 185 u8 podr_lcdctlh; /* 0x10 */ 186 u8 podr_lcdctll; /* 0x11 */ 187 #else 188 u16 res0C; /* 0x0C - 0x0D */ 189 u8 podr_fech; /* 0x0E */ 190 u8 podr_fecl; /* 0x0F */ 191 u16 res10[3]; /* 0x10 - 0x15 */ 192 #endif 193 194 /* Port Data Direction Registers */ 195 #ifdef CONFIG_M5329 196 u16 res12; /* 0x12 - 0x13 */ 197 u8 pddr_fech; /* 0x14 */ 198 u8 pddr_fecl; /* 0x15 */ 199 #endif 200 u8 pddr_ssi; /* 0x16 */ 201 u8 pddr_busctl; /* 0x17 */ 202 u8 pddr_be; /* 0x18 */ 203 u8 pddr_cs; /* 0x19 */ 204 u8 pddr_pwm; /* 0x1A */ 205 u8 pddr_feci2c; /* 0x1B */ 206 u8 res1C; /* 0x1C */ 207 u8 pddr_uart; /* 0x1D */ 208 u8 pddr_qspi; /* 0x1E */ 209 u8 pddr_timer; /* 0x1F */ 210 #ifdef CONFIG_M5329 211 u8 res20; /* 0x20 */ 212 u8 pddr_lcddatah; /* 0x21 */ 213 u8 pddr_lcddatam; /* 0x22 */ 214 u8 pddr_lcddatal; /* 0x23 */ 215 u8 pddr_lcdctlh; /* 0x24 */ 216 u8 pddr_lcdctll; /* 0x25 */ 217 u16 res26; /* 0x26 - 0x27 */ 218 #else 219 u16 res20; /* 0x20 - 0x21 */ 220 u8 pddr_fech; /* 0x22 */ 221 u8 pddr_fecl; /* 0x23 */ 222 u16 res24[3]; /* 0x24 - 0x29 */ 223 #endif 224 225 /* Port Data Direction Registers */ 226 #ifdef CONFIG_M5329 227 u8 ppd_fech; /* 0x28 */ 228 u8 ppd_fecl; /* 0x29 */ 229 #endif 230 u8 ppd_ssi; /* 0x2A */ 231 u8 ppd_busctl; /* 0x2B */ 232 u8 ppd_be; /* 0x2C */ 233 u8 ppd_cs; /* 0x2D */ 234 u8 ppd_pwm; /* 0x2E */ 235 u8 ppd_feci2c; /* 0x2F */ 236 u8 res30; /* 0x30 */ 237 u8 ppd_uart; /* 0x31 */ 238 u8 ppd_qspi; /* 0x32 */ 239 u8 ppd_timer; /* 0x33 */ 240 #ifdef CONFIG_M5329 241 u8 res34; /* 0x34 */ 242 u8 ppd_lcddatah; /* 0x35 */ 243 u8 ppd_lcddatam; /* 0x36 */ 244 u8 ppd_lcddatal; /* 0x37 */ 245 u8 ppd_lcdctlh; /* 0x38 */ 246 u8 ppd_lcdctll; /* 0x39 */ 247 u16 res3A; /* 0x3A - 0x3B */ 248 #else 249 u16 res34; /* 0x34 - 0x35 */ 250 u8 ppd_fech; /* 0x36 */ 251 u8 ppd_fecl; /* 0x37 */ 252 u16 res38[3]; /* 0x38 - 0x3D */ 253 #endif 254 255 /* Port Clear Output Data Registers */ 256 #ifdef CONFIG_M5329 257 u8 res3C; /* 0x3C */ 258 u8 pclrr_fech; /* 0x3D */ 259 u8 pclrr_fecl; /* 0x3E */ 260 #else 261 u8 pclrr_ssi; /* 0x3E */ 262 #endif 263 u8 pclrr_busctl; /* 0x3F */ 264 u8 pclrr_be; /* 0x40 */ 265 u8 pclrr_cs; /* 0x41 */ 266 u8 pclrr_pwm; /* 0x42 */ 267 u8 pclrr_feci2c; /* 0x43 */ 268 u8 res44; /* 0x44 */ 269 u8 pclrr_uart; /* 0x45 */ 270 u8 pclrr_qspi; /* 0x46 */ 271 u8 pclrr_timer; /* 0x47 */ 272 #ifdef CONFIG_M5329 273 u8 pclrr_lcddatah; /* 0x48 */ 274 u8 pclrr_lcddatam; /* 0x49 */ 275 u8 pclrr_lcddatal; /* 0x4A */ 276 u8 pclrr_ssi; /* 0x4B */ 277 u8 pclrr_lcdctlh; /* 0x4C */ 278 u8 pclrr_lcdctll; /* 0x4D */ 279 u16 res4E; /* 0x4E - 0x4F */ 280 #else 281 u16 res48; /* 0x48 - 0x49 */ 282 u8 pclrr_fech; /* 0x4A */ 283 u8 pclrr_fecl; /* 0x4B */ 284 u8 res4C[5]; /* 0x4C - 0x50 */ 285 #endif 286 287 /* Pin Assignment Registers */ 288 #ifdef CONFIG_M5329 289 u8 par_fec; /* 0x50 */ 290 #endif 291 u8 par_pwm; /* 0x51 */ 292 u8 par_busctl; /* 0x52 */ 293 u8 par_feci2c; /* 0x53 */ 294 u8 par_be; /* 0x54 */ 295 u8 par_cs; /* 0x55 */ 296 u16 par_ssi; /* 0x56 */ 297 u16 par_uart; /* 0x58 */ 298 u16 par_qspi; /* 0x5A */ 299 u8 par_timer; /* 0x5C */ 300 #ifdef CONFIG_M5329 301 u8 par_lcddata; /* 0x5D */ 302 u16 par_lcdctl; /* 0x5E */ 303 #else 304 u8 par_fec; /* 0x5D */ 305 u16 res5E; /* 0x5E - 0x5F */ 306 #endif 307 u16 par_irq; /* 0x60 */ 308 u16 res62; /* 0x62 - 0x63 */ 309 310 /* Mode Select Control Registers */ 311 u8 mscr_flexbus; /* 0x64 */ 312 u8 mscr_sdram; /* 0x65 */ 313 u16 res66; /* 0x66 - 0x67 */ 314 315 /* Drive Strength Control Registers */ 316 u8 dscr_i2c; /* 0x68 */ 317 u8 dscr_pwm; /* 0x69 */ 318 u8 dscr_fec; /* 0x6A */ 319 u8 dscr_uart; /* 0x6B */ 320 u8 dscr_qspi; /* 0x6C */ 321 u8 dscr_timer; /* 0x6D */ 322 u8 dscr_ssi; /* 0x6E */ 323 #ifdef CONFIG_M5329 324 u8 dscr_lcd; /* 0x6F */ 325 #else 326 u8 res6F; /* 0x6F */ 327 #endif 328 u8 dscr_debug; /* 0x70 */ 329 u8 dscr_clkrst; /* 0x71 */ 330 u8 dscr_irq; /* 0x72 */ 331 } gpio_t; 332 333 /* USB OTG module registers */ 334 typedef struct usb_otg { 335 u32 id; /* 0x000 Identification Register */ 336 u32 hwgeneral; /* 0x004 General HW Parameters */ 337 u32 hwhost; /* 0x008 Host HW Parameters */ 338 u32 hwdev; /* 0x00C Device HW parameters */ 339 u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */ 340 u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */ 341 u32 res1[58]; /* 0x18 - 0xFF */ 342 u8 caplength; /* 0x100 Capability Register Length */ 343 u8 res2; /* 0x101 */ 344 u16 hciver; /* 0x102 Host Interface Version Number */ 345 u32 hcsparams; /* 0x104 Host Structural Parameters */ 346 u32 hccparams; /* 0x108 Host Capability Parameters */ 347 u32 res3[5]; /* 0x10C - 0x11F */ 348 u16 dciver; /* 0x120 Device Interface Version Number */ 349 u16 res4; /* 0x122 */ 350 u32 dccparams; /* 0x124 Device Capability Parameters */ 351 u32 res5[6]; /* 0x128 - 0x13F */ 352 u32 cmd; /* 0x140 USB Command */ 353 u32 sts; /* 0x144 USB Status */ 354 u32 intr; /* 0x148 USB Interrupt Enable */ 355 u32 frindex; /* 0x14C USB Frame Index */ 356 u32 res6; /* 0x150 */ 357 u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */ 358 u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */ 359 u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */ 360 u32 burstsize; /* 0x160 Master Interface Data Burst Size */ 361 u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */ 362 u32 res7[6]; /* 0x168 - 0x17F */ 363 u32 cfgflag; /* 0x180 Configure Flag Register */ 364 u32 portsc1; /* 0x184 Port Status/Control */ 365 u32 res8[7]; /* 0x188 - 0x1A3 */ 366 u32 otgsc; /* 0x1A4 On The Go Status and Control */ 367 u32 mode; /* 0x1A8 USB mode register */ 368 u32 eptsetstat; /* 0x1AC Endpoint Setup status */ 369 u32 eptprime; /* 0x1B0 Endpoint initialization */ 370 u32 eptflush; /* 0x1B4 Endpoint de-initialize */ 371 u32 eptstat; /* 0x1B8 Endpoint status */ 372 u32 eptcomplete; /* 0x1BC Endpoint Complete */ 373 u32 eptctrl0; /* 0x1C0 Endpoint control 0 */ 374 u32 eptctrl1; /* 0x1C4 Endpoint control 1 */ 375 u32 eptctrl2; /* 0x1C8 Endpoint control 2 */ 376 u32 eptctrl3; /* 0x1CC Endpoint control 3 */ 377 } usbotg_t; 378 379 /* SDRAM controller registers */ 380 typedef struct sdram_ctrl { 381 u32 mode; /* 0x00 Mode/Extended Mode register */ 382 u32 ctrl; /* 0x04 Control register */ 383 u32 cfg1; /* 0x08 Configuration register 1 */ 384 u32 cfg2; /* 0x0C Configuration register 2 */ 385 u32 res1[64]; /* 0x10 - 0x10F */ 386 u32 cs0; /* 0x110 Chip Select 0 Configuration */ 387 u32 cs1; /* 0x114 Chip Select 1 Configuration */ 388 } sdram_t; 389 390 /* Clock Module registers */ 391 typedef struct pll_ctrl { 392 u8 podr; /* 0x00 Output Divider Register */ 393 u8 res1[3]; 394 u8 pcr; /* 0x04 Control Register */ 395 u8 res2[3]; 396 u8 pmdr; /* 0x08 Modulation Divider Register */ 397 u8 res3[3]; 398 u8 pfdr; /* 0x0C Feedback Divider Register */ 399 u8 res4[3]; 400 } pll_t; 401 402 #endif /* __IMMAP_5329__ */ 403