1 /* 2 * ColdFire Internal Memory Map and Defines 3 * 4 * Copyright 2004-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __IMMAP_H 11 #define __IMMAP_H 12 13 #if defined(CONFIG_MCF520x) 14 #include <asm/immap_520x.h> 15 #include <asm/m520x.h> 16 17 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 18 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 19 20 /* Timer */ 21 #ifdef CONFIG_MCFTMR 22 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 23 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 24 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 25 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 26 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 27 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 28 #define CONFIG_SYS_TMRINTR_PRI (6) 29 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 30 #endif 31 32 #ifdef CONFIG_MCFPIT 33 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 34 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 35 #define CONFIG_SYS_PIT_PRESCALE (6) 36 #endif 37 38 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 39 #define CONFIG_SYS_NUM_IRQS (128) 40 #endif /* CONFIG_M520x */ 41 42 #ifdef CONFIG_M52277 43 #include <asm/immap_5227x.h> 44 #include <asm/m5227x.h> 45 46 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 47 48 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 49 50 #ifdef CONFIG_LCD 51 #define CONFIG_SYS_LCD_BASE (MMAP_LCD) 52 #endif 53 54 /* Timer */ 55 #ifdef CONFIG_MCFTMR 56 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 57 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 58 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 59 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 60 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 61 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 62 #define CONFIG_SYS_TMRINTR_PRI (6) 63 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 64 #endif 65 66 #ifdef CONFIG_MCFPIT 67 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 68 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 69 #define CONFIG_SYS_PIT_PRESCALE (6) 70 #endif 71 72 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 73 #define CONFIG_SYS_NUM_IRQS (128) 74 #endif /* CONFIG_M52277 */ 75 76 #ifdef CONFIG_M5235 77 #include <asm/immap_5235.h> 78 #include <asm/m5235.h> 79 80 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 81 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 82 83 /* Timer */ 84 #ifdef CONFIG_MCFTMR 85 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 86 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 87 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 88 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 89 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 90 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 91 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 92 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 93 #endif 94 95 #ifdef CONFIG_MCFPIT 96 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 97 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 98 #define CONFIG_SYS_PIT_PRESCALE (6) 99 #endif 100 101 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 102 #define CONFIG_SYS_NUM_IRQS (128) 103 #endif /* CONFIG_M5235 */ 104 105 #ifdef CONFIG_M5249 106 #include <asm/immap_5249.h> 107 #include <asm/m5249.h> 108 109 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 110 111 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 112 #define CONFIG_SYS_NUM_IRQS (64) 113 114 /* Timer */ 115 #ifdef CONFIG_MCFTMR 116 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 117 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 118 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 119 #define CONFIG_SYS_TMRINTR_NO (31) 120 #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 121 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 122 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 123 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 124 #endif 125 #endif /* CONFIG_M5249 */ 126 127 #ifdef CONFIG_M5253 128 #include <asm/immap_5253.h> 129 #include <asm/m5249.h> 130 #include <asm/m5253.h> 131 132 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 133 134 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 135 #define CONFIG_SYS_NUM_IRQS (64) 136 137 /* Timer */ 138 #ifdef CONFIG_MCFTMR 139 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 140 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 141 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 142 #define CONFIG_SYS_TMRINTR_NO (27) 143 #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 144 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 145 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) 146 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 147 #endif 148 #endif /* CONFIG_M5253 */ 149 150 #ifdef CONFIG_M5271 151 #include <asm/immap_5271.h> 152 #include <asm/m5271.h> 153 154 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 155 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 156 157 /* Timer */ 158 #ifdef CONFIG_MCFTMR 159 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 160 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 161 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 162 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 163 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 164 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 165 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ 166 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 167 #endif 168 169 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 170 #define CONFIG_SYS_NUM_IRQS (128) 171 #endif /* CONFIG_M5271 */ 172 173 #ifdef CONFIG_M5272 174 #include <asm/immap_5272.h> 175 #include <asm/m5272.h> 176 177 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 178 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 179 180 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 181 #define CONFIG_SYS_NUM_IRQS (64) 182 183 /* Timer */ 184 #ifdef CONFIG_MCFTMR 185 #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) 186 #define CONFIG_SYS_TMR_BASE (MMAP_TMR3) 187 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) 188 #define CONFIG_SYS_TMRINTR_NO (INT_TMR3) 189 #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) 190 #define CONFIG_SYS_TMRINTR_PEND (0) 191 #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) 192 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 193 #endif 194 #endif /* CONFIG_M5272 */ 195 196 #ifdef CONFIG_M5275 197 #include <asm/immap_5275.h> 198 #include <asm/m5275.h> 199 200 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 201 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 202 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 203 204 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 205 #define CONFIG_SYS_NUM_IRQS (192) 206 207 /* Timer */ 208 #ifdef CONFIG_MCFTMR 209 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 210 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 211 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 212 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 213 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 214 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 215 #define CONFIG_SYS_TMRINTR_PRI (0x1E) 216 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 217 #endif 218 #endif /* CONFIG_M5275 */ 219 220 #ifdef CONFIG_M5282 221 #include <asm/immap_5282.h> 222 #include <asm/m5282.h> 223 224 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 225 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 226 227 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 228 #define CONFIG_SYS_NUM_IRQS (128) 229 230 /* Timer */ 231 #ifdef CONFIG_MCFTMR 232 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 233 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 234 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 235 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 236 #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) 237 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 238 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 239 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 240 #endif 241 #endif /* CONFIG_M5282 */ 242 243 #ifdef CONFIG_M5307 244 #include <asm/immap_5307.h> 245 #include <asm/m5307.h> 246 247 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 248 (CONFIG_SYS_UART_PORT * 0x40)) 249 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 250 #define CONFIG_SYS_NUM_IRQS (64) 251 252 /* Timer */ 253 #ifdef CONFIG_MCFTMR 254 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 255 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 256 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ 257 (CONFIG_SYS_INTR_BASE))->ipr) 258 #define CONFIG_SYS_TMRINTR_NO (31) 259 #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 260 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 261 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ 262 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 263 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 264 #endif 265 #endif /* CONFIG_M5307 */ 266 267 #if defined(CONFIG_MCF5301x) 268 #include <asm/immap_5301x.h> 269 #include <asm/m5301x.h> 270 271 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 272 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 273 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 274 275 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 276 277 /* Timer */ 278 #ifdef CONFIG_MCFTMR 279 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 280 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 281 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 282 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 283 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 284 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 285 #define CONFIG_SYS_TMRINTR_PRI (6) 286 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 287 #endif 288 289 #ifdef CONFIG_MCFPIT 290 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 291 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 292 #define CONFIG_SYS_PIT_PRESCALE (6) 293 #endif 294 295 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 296 #define CONFIG_SYS_NUM_IRQS (128) 297 #endif /* CONFIG_M5301x */ 298 299 #if defined(CONFIG_M5329) || defined(CONFIG_M5373) 300 #include <asm/immap_5329.h> 301 #include <asm/m5329.h> 302 303 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 304 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 305 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 306 307 /* Timer */ 308 #ifdef CONFIG_MCFTMR 309 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 310 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 311 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 312 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 313 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 314 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 315 #define CONFIG_SYS_TMRINTR_PRI (6) 316 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 317 #endif 318 319 #ifdef CONFIG_MCFPIT 320 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 321 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 322 #define CONFIG_SYS_PIT_PRESCALE (6) 323 #endif 324 325 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 326 #define CONFIG_SYS_NUM_IRQS (128) 327 #endif /* CONFIG_M5329 && CONFIG_M5373 */ 328 329 #if defined(CONFIG_M54418) 330 #include <asm/immap_5441x.h> 331 #include <asm/m5441x.h> 332 333 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 334 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 335 336 #if (CONFIG_SYS_UART_PORT < 4) 337 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 338 (CONFIG_SYS_UART_PORT * 0x4000)) 339 #else 340 #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ 341 ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) 342 #endif 343 344 #define MMAP_DSPI MMAP_DSPI0 345 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 346 347 /* Timer */ 348 #ifdef CONFIG_MCFTMR 349 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 350 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 351 #define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 352 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 353 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 354 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 355 #define CONFIG_SYS_TMRINTR_PRI (6) 356 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 357 #endif 358 359 #ifdef CONFIG_MCFPIT 360 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 361 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 362 #define CONFIG_SYS_PIT_PRESCALE (6) 363 #endif 364 365 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 366 #define CONFIG_SYS_NUM_IRQS (128) 367 368 #endif /* CONFIG_M54418 */ 369 370 #if defined(CONFIG_M54451) || defined(CONFIG_M54455) 371 #include <asm/immap_5445x.h> 372 #include <asm/m5445x.h> 373 374 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 375 #if defined(CONFIG_M54455EVB) 376 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 377 #endif 378 379 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 380 381 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 382 383 /* Timer */ 384 #ifdef CONFIG_MCFTMR 385 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 386 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 387 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 388 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 389 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 390 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 391 #define CONFIG_SYS_TMRINTR_PRI (6) 392 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 393 #endif 394 395 #ifdef CONFIG_MCFPIT 396 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) 397 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) 398 #define CONFIG_SYS_PIT_PRESCALE (6) 399 #endif 400 401 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 402 #define CONFIG_SYS_NUM_IRQS (128) 403 404 #ifdef CONFIG_PCI 405 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 406 #define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) 407 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 408 #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) 409 #endif 410 #endif /* CONFIG_M54451 || CONFIG_M54455 */ 411 412 #ifdef CONFIG_M547x 413 #include <asm/immap_547x_8x.h> 414 #include <asm/m547x_8x.h> 415 416 #ifdef CONFIG_FSLDMAFEC 417 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 418 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 419 420 #define FEC0_RX_TASK 0 421 #define FEC0_TX_TASK 1 422 #define FEC0_RX_PRIORITY 6 423 #define FEC0_TX_PRIORITY 7 424 #define FEC0_RX_INIT 16 425 #define FEC0_TX_INIT 17 426 #define FEC1_RX_TASK 2 427 #define FEC1_TX_TASK 3 428 #define FEC1_RX_PRIORITY 6 429 #define FEC1_TX_PRIORITY 7 430 #define FEC1_RX_INIT 30 431 #define FEC1_TX_INIT 31 432 #endif 433 434 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 435 436 #ifdef CONFIG_SLTTMR 437 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 438 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 439 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 440 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 441 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 442 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 443 #define CONFIG_SYS_TMRINTR_PRI (0x1E) 444 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 445 #endif 446 447 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 448 #define CONFIG_SYS_NUM_IRQS (128) 449 450 #ifdef CONFIG_PCI 451 #define CONFIG_SYS_PCI_BAR0 (0x40000000) 452 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 453 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 454 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 455 #endif 456 #endif /* CONFIG_M547x */ 457 458 #ifdef CONFIG_M548x 459 #include <asm/immap_547x_8x.h> 460 #include <asm/m547x_8x.h> 461 462 #ifdef CONFIG_FSLDMAFEC 463 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 464 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 465 466 #define FEC0_RX_TASK 0 467 #define FEC0_TX_TASK 1 468 #define FEC0_RX_PRIORITY 6 469 #define FEC0_TX_PRIORITY 7 470 #define FEC0_RX_INIT 16 471 #define FEC0_TX_INIT 17 472 #define FEC1_RX_TASK 2 473 #define FEC1_TX_TASK 3 474 #define FEC1_RX_PRIORITY 6 475 #define FEC1_TX_PRIORITY 7 476 #define FEC1_RX_INIT 30 477 #define FEC1_TX_INIT 31 478 #endif 479 480 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 481 482 /* Timer */ 483 #ifdef CONFIG_SLTTMR 484 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 485 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 486 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 487 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 488 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 489 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 490 #define CONFIG_SYS_TMRINTR_PRI (0x1E) 491 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 492 #endif 493 494 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 495 #define CONFIG_SYS_NUM_IRQS (128) 496 497 #ifdef CONFIG_PCI 498 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 499 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 500 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 501 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 502 #endif 503 #endif /* CONFIG_M548x */ 504 505 #endif /* __IMMAP_H */ 506