1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser /* 3819833afSPeter Tyser * fec.h -- Fast Ethernet Controller definitions 4819833afSPeter Tyser * 5819833afSPeter Tyser * Some definitions copied from commproc.h for MPC8xx: 6819833afSPeter Tyser * MPC8xx Communication Processor Module. 7819833afSPeter Tyser * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 8819833afSPeter Tyser * 9819833afSPeter Tyser * Add FEC Structure and definitions 10819833afSPeter Tyser * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 11819833afSPeter Tyser * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 12819833afSPeter Tyser */ 13819833afSPeter Tyser 14819833afSPeter Tyser #ifndef fec_h 15819833afSPeter Tyser #define fec_h 16819833afSPeter Tyser 17dfcc496eSJoe Hershberger #include <phy.h> 18dfcc496eSJoe Hershberger 19819833afSPeter Tyser /* Buffer descriptors used FEC. 20819833afSPeter Tyser */ 21819833afSPeter Tyser typedef struct cpm_buf_desc { 22819833afSPeter Tyser ushort cbd_sc; /* Status and Control */ 23819833afSPeter Tyser ushort cbd_datlen; /* Data length in buffer */ 24819833afSPeter Tyser uint cbd_bufaddr; /* Buffer address in host memory */ 25819833afSPeter Tyser } cbd_t; 26819833afSPeter Tyser 2716263087SMike Williams #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 28819833afSPeter Tyser #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 29819833afSPeter Tyser #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 30819833afSPeter Tyser #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 31819833afSPeter Tyser #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 32819833afSPeter Tyser #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 33819833afSPeter Tyser #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 34819833afSPeter Tyser #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 35819833afSPeter Tyser #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 36819833afSPeter Tyser #define BD_SC_BR ((ushort)0x0020) /* Break received */ 37819833afSPeter Tyser #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 38819833afSPeter Tyser #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 39819833afSPeter Tyser #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 40819833afSPeter Tyser #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ 41819833afSPeter Tyser 42819833afSPeter Tyser /* Buffer descriptor control/status used by Ethernet receive. 43819833afSPeter Tyser */ 44819833afSPeter Tyser #define BD_ENET_RX_EMPTY ((ushort)0x8000) 45819833afSPeter Tyser #define BD_ENET_RX_RO1 ((ushort)0x4000) 46819833afSPeter Tyser #define BD_ENET_RX_WRAP ((ushort)0x2000) 47819833afSPeter Tyser #define BD_ENET_RX_INTR ((ushort)0x1000) 48819833afSPeter Tyser #define BD_ENET_RX_RO2 BD_ENET_RX_INTR 49819833afSPeter Tyser #define BD_ENET_RX_LAST ((ushort)0x0800) 50819833afSPeter Tyser #define BD_ENET_RX_FIRST ((ushort)0x0400) 51819833afSPeter Tyser #define BD_ENET_RX_MISS ((ushort)0x0100) 52819833afSPeter Tyser #define BD_ENET_RX_BC ((ushort)0x0080) 53819833afSPeter Tyser #define BD_ENET_RX_MC ((ushort)0x0040) 54819833afSPeter Tyser #define BD_ENET_RX_LG ((ushort)0x0020) 55819833afSPeter Tyser #define BD_ENET_RX_NO ((ushort)0x0010) 56819833afSPeter Tyser #define BD_ENET_RX_SH ((ushort)0x0008) 57819833afSPeter Tyser #define BD_ENET_RX_CR ((ushort)0x0004) 58819833afSPeter Tyser #define BD_ENET_RX_OV ((ushort)0x0002) 59819833afSPeter Tyser #define BD_ENET_RX_CL ((ushort)0x0001) 60819833afSPeter Tyser #define BD_ENET_RX_TR BD_ENET_RX_CL 61819833afSPeter Tyser #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 62819833afSPeter Tyser 63819833afSPeter Tyser /* Buffer descriptor control/status used by Ethernet transmit. 64819833afSPeter Tyser */ 65819833afSPeter Tyser #define BD_ENET_TX_READY ((ushort)0x8000) 66819833afSPeter Tyser #define BD_ENET_TX_PAD ((ushort)0x4000) 67819833afSPeter Tyser #define BD_ENET_TX_TO1 BD_ENET_TX_PAD 68819833afSPeter Tyser #define BD_ENET_TX_WRAP ((ushort)0x2000) 69819833afSPeter Tyser #define BD_ENET_TX_INTR ((ushort)0x1000) 70819833afSPeter Tyser #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ 71819833afSPeter Tyser #define BD_ENET_TX_LAST ((ushort)0x0800) 72819833afSPeter Tyser #define BD_ENET_TX_TC ((ushort)0x0400) 73819833afSPeter Tyser #define BD_ENET_TX_DEF ((ushort)0x0200) 74819833afSPeter Tyser #define BD_ENET_TX_ABC BD_ENET_TX_DEF 75819833afSPeter Tyser #define BD_ENET_TX_HB ((ushort)0x0100) 76819833afSPeter Tyser #define BD_ENET_TX_LC ((ushort)0x0080) 77819833afSPeter Tyser #define BD_ENET_TX_RL ((ushort)0x0040) 78819833afSPeter Tyser #define BD_ENET_TX_RCMASK ((ushort)0x003c) 79819833afSPeter Tyser #define BD_ENET_TX_UN ((ushort)0x0002) 80819833afSPeter Tyser #define BD_ENET_TX_CSL ((ushort)0x0001) 81819833afSPeter Tyser #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 82819833afSPeter Tyser 83819833afSPeter Tyser /********************************************************************* 84819833afSPeter Tyser * Fast Ethernet Controller (FEC) 85819833afSPeter Tyser *********************************************************************/ 86819833afSPeter Tyser /* FEC private information */ 87819833afSPeter Tyser struct fec_info_s { 88819833afSPeter Tyser int index; 89819833afSPeter Tyser u32 iobase; 90819833afSPeter Tyser u32 pinmux; 91819833afSPeter Tyser u32 miibase; 92819833afSPeter Tyser int phy_addr; 93819833afSPeter Tyser int dup_spd; 94819833afSPeter Tyser char *phy_name; 95819833afSPeter Tyser int phyname_init; 96819833afSPeter Tyser cbd_t *rxbd; /* Rx BD */ 97819833afSPeter Tyser cbd_t *txbd; /* Tx BD */ 98819833afSPeter Tyser uint rxIdx; 99819833afSPeter Tyser uint txIdx; 100819833afSPeter Tyser char *txbuf; 101819833afSPeter Tyser int initialized; 102819833afSPeter Tyser struct fec_info_s *next; 103819833afSPeter Tyser }; 104819833afSPeter Tyser 105819833afSPeter Tyser #ifdef CONFIG_MCFFEC 106819833afSPeter Tyser /* Register read/write struct */ 107819833afSPeter Tyser typedef struct fec { 108819833afSPeter Tyser #ifdef CONFIG_M5272 109819833afSPeter Tyser u32 ecr; /* 0x00 */ 110819833afSPeter Tyser u32 eir; /* 0x04 */ 111819833afSPeter Tyser u32 eimr; /* 0x08 */ 112819833afSPeter Tyser u32 ivsr; /* 0x0C */ 113819833afSPeter Tyser u32 rdar; /* 0x10 */ 114819833afSPeter Tyser u32 tdar; /* 0x14 */ 115819833afSPeter Tyser u8 resv1[0x28]; /* 0x18 */ 116819833afSPeter Tyser u32 mmfr; /* 0x40 */ 117819833afSPeter Tyser u32 mscr; /* 0x44 */ 118819833afSPeter Tyser u8 resv2[0x44]; /* 0x48 */ 119819833afSPeter Tyser u32 frbr; /* 0x8C */ 120819833afSPeter Tyser u32 frsr; /* 0x90 */ 121819833afSPeter Tyser u8 resv3[0x10]; /* 0x94 */ 122819833afSPeter Tyser u32 tfwr; /* 0xA4 */ 123819833afSPeter Tyser u32 res4; /* 0xA8 */ 124819833afSPeter Tyser u32 tfsr; /* 0xAC */ 125819833afSPeter Tyser u8 resv4[0x50]; /* 0xB0 */ 126819833afSPeter Tyser u32 opd; /* 0x100 - dummy */ 127819833afSPeter Tyser u32 rcr; /* 0x104 */ 128819833afSPeter Tyser u32 mibc; /* 0x108 */ 129819833afSPeter Tyser u8 resv5[0x38]; /* 0x10C */ 130819833afSPeter Tyser u32 tcr; /* 0x144 */ 131819833afSPeter Tyser u8 resv6[0x270]; /* 0x148 */ 132819833afSPeter Tyser u32 iaur; /* 0x3B8 - dummy */ 133819833afSPeter Tyser u32 ialr; /* 0x3BC - dummy */ 134819833afSPeter Tyser u32 palr; /* 0x3C0 */ 135819833afSPeter Tyser u32 paur; /* 0x3C4 */ 136819833afSPeter Tyser u32 gaur; /* 0x3C8 */ 137819833afSPeter Tyser u32 galr; /* 0x3CC */ 138819833afSPeter Tyser u32 erdsr; /* 0x3D0 */ 139819833afSPeter Tyser u32 etdsr; /* 0x3D4 */ 140819833afSPeter Tyser u32 emrbr; /* 0x3D8 */ 141819833afSPeter Tyser u8 resv12[0x74]; /* 0x18C */ 142819833afSPeter Tyser #else 143819833afSPeter Tyser u8 resv0[0x4]; 144819833afSPeter Tyser u32 eir; 145819833afSPeter Tyser u32 eimr; 146819833afSPeter Tyser u8 resv1[0x4]; 147819833afSPeter Tyser u32 rdar; 148819833afSPeter Tyser u32 tdar; 149819833afSPeter Tyser u8 resv2[0xC]; 150819833afSPeter Tyser u32 ecr; 151819833afSPeter Tyser u8 resv3[0x18]; 152819833afSPeter Tyser u32 mmfr; 153819833afSPeter Tyser u32 mscr; 154819833afSPeter Tyser u8 resv4[0x1C]; 155819833afSPeter Tyser u32 mibc; 156819833afSPeter Tyser u8 resv5[0x1C]; 157819833afSPeter Tyser u32 rcr; 158819833afSPeter Tyser u8 resv6[0x3C]; 159819833afSPeter Tyser u32 tcr; 160819833afSPeter Tyser u8 resv7[0x1C]; 161819833afSPeter Tyser u32 palr; 162819833afSPeter Tyser u32 paur; 163819833afSPeter Tyser u32 opd; 164819833afSPeter Tyser u8 resv8[0x28]; 165819833afSPeter Tyser u32 iaur; 166819833afSPeter Tyser u32 ialr; 167819833afSPeter Tyser u32 gaur; 168819833afSPeter Tyser u32 galr; 169819833afSPeter Tyser u8 resv9[0x1C]; 170819833afSPeter Tyser u32 tfwr; 171819833afSPeter Tyser u8 resv10[0x4]; 172819833afSPeter Tyser u32 frbr; 173819833afSPeter Tyser u32 frsr; 174819833afSPeter Tyser u8 resv11[0x2C]; 175819833afSPeter Tyser u32 erdsr; 176819833afSPeter Tyser u32 etdsr; 177819833afSPeter Tyser u32 emrbr; 178819833afSPeter Tyser u8 resv12[0x74]; 179819833afSPeter Tyser #endif 180819833afSPeter Tyser 181819833afSPeter Tyser u32 rmon_t_drop; 182819833afSPeter Tyser u32 rmon_t_packets; 183819833afSPeter Tyser u32 rmon_t_bc_pkt; 184819833afSPeter Tyser u32 rmon_t_mc_pkt; 185819833afSPeter Tyser u32 rmon_t_crc_align; 186819833afSPeter Tyser u32 rmon_t_undersize; 187819833afSPeter Tyser u32 rmon_t_oversize; 188819833afSPeter Tyser u32 rmon_t_frag; 189819833afSPeter Tyser u32 rmon_t_jab; 190819833afSPeter Tyser u32 rmon_t_col; 191819833afSPeter Tyser u32 rmon_t_p64; 192819833afSPeter Tyser u32 rmon_t_p65to127; 193819833afSPeter Tyser u32 rmon_t_p128to255; 194819833afSPeter Tyser u32 rmon_t_p256to511; 195819833afSPeter Tyser u32 rmon_t_p512to1023; 196819833afSPeter Tyser u32 rmon_t_p1024to2047; 197819833afSPeter Tyser u32 rmon_t_p_gte2048; 198819833afSPeter Tyser u32 rmon_t_octets; 199819833afSPeter Tyser 200819833afSPeter Tyser u32 ieee_t_drop; 201819833afSPeter Tyser u32 ieee_t_frame_ok; 202819833afSPeter Tyser u32 ieee_t_1col; 203819833afSPeter Tyser u32 ieee_t_mcol; 204819833afSPeter Tyser u32 ieee_t_def; 205819833afSPeter Tyser u32 ieee_t_lcol; 206819833afSPeter Tyser u32 ieee_t_excol; 207819833afSPeter Tyser u32 ieee_t_macerr; 208819833afSPeter Tyser u32 ieee_t_cserr; 209819833afSPeter Tyser u32 ieee_t_sqe; 210819833afSPeter Tyser u32 ieee_t_fdxfc; 211819833afSPeter Tyser u32 ieee_t_octets_ok; 212819833afSPeter Tyser u8 resv13[0x8]; 213819833afSPeter Tyser 214819833afSPeter Tyser u32 rmon_r_drop; 215819833afSPeter Tyser u32 rmon_r_packets; 216819833afSPeter Tyser u32 rmon_r_bc_pkt; 217819833afSPeter Tyser u32 rmon_r_mc_pkt; 218819833afSPeter Tyser u32 rmon_r_crc_align; 219819833afSPeter Tyser u32 rmon_r_undersize; 220819833afSPeter Tyser u32 rmon_r_oversize; 221819833afSPeter Tyser u32 rmon_r_frag; 222819833afSPeter Tyser u32 rmon_r_jab; 223819833afSPeter Tyser u32 rmon_r_resvd_0; 224819833afSPeter Tyser u32 rmon_r_p64; 225819833afSPeter Tyser u32 rmon_r_p65to127; 226819833afSPeter Tyser u32 rmon_r_p128to255; 227819833afSPeter Tyser u32 rmon_r_p256to511; 228819833afSPeter Tyser u32 rmon_r_p512to1023; 229819833afSPeter Tyser u32 rmon_r_p1024to2047; 230819833afSPeter Tyser u32 rmon_r_p_gte2048; 231819833afSPeter Tyser u32 rmon_r_octets; 232819833afSPeter Tyser 233819833afSPeter Tyser u32 ieee_r_drop; 234819833afSPeter Tyser u32 ieee_r_frame_ok; 235819833afSPeter Tyser u32 ieee_r_crc; 236819833afSPeter Tyser u32 ieee_r_align; 237819833afSPeter Tyser u32 ieee_r_macerr; 238819833afSPeter Tyser u32 ieee_r_fdxfc; 239819833afSPeter Tyser u32 ieee_r_octets_ok; 240819833afSPeter Tyser } fec_t; 241819833afSPeter Tyser #endif /* CONFIG_MCFFEC */ 242819833afSPeter Tyser 243819833afSPeter Tyser /********************************************************************* 244819833afSPeter Tyser * Fast Ethernet Controller (FEC) 245819833afSPeter Tyser *********************************************************************/ 246819833afSPeter Tyser /* Bit definitions and macros for FEC_EIR */ 247819833afSPeter Tyser #define FEC_EIR_CLEAR_ALL (0xFFF80000) 248819833afSPeter Tyser #define FEC_EIR_HBERR (0x80000000) 249819833afSPeter Tyser #define FEC_EIR_BABR (0x40000000) 250819833afSPeter Tyser #define FEC_EIR_BABT (0x20000000) 251819833afSPeter Tyser #define FEC_EIR_GRA (0x10000000) 252819833afSPeter Tyser #define FEC_EIR_TXF (0x08000000) 253819833afSPeter Tyser #define FEC_EIR_TXB (0x04000000) 254819833afSPeter Tyser #define FEC_EIR_RXF (0x02000000) 255819833afSPeter Tyser #define FEC_EIR_RXB (0x01000000) 256819833afSPeter Tyser #define FEC_EIR_MII (0x00800000) 257819833afSPeter Tyser #define FEC_EIR_EBERR (0x00400000) 258819833afSPeter Tyser #define FEC_EIR_LC (0x00200000) 259819833afSPeter Tyser #define FEC_EIR_RL (0x00100000) 260819833afSPeter Tyser #define FEC_EIR_UN (0x00080000) 261819833afSPeter Tyser 262819833afSPeter Tyser /* Bit definitions and macros for FEC_RDAR */ 263819833afSPeter Tyser #define FEC_RDAR_R_DES_ACTIVE (0x01000000) 264819833afSPeter Tyser 265819833afSPeter Tyser /* Bit definitions and macros for FEC_TDAR */ 266819833afSPeter Tyser #define FEC_TDAR_X_DES_ACTIVE (0x01000000) 267819833afSPeter Tyser 268819833afSPeter Tyser /* Bit definitions and macros for FEC_ECR */ 269819833afSPeter Tyser #define FEC_ECR_ETHER_EN (0x00000002) 270819833afSPeter Tyser #define FEC_ECR_RESET (0x00000001) 271819833afSPeter Tyser 272819833afSPeter Tyser /* Bit definitions and macros for FEC_MMFR */ 273819833afSPeter Tyser #define FEC_MMFR_DATA(x) (((x)&0xFFFF)) 274819833afSPeter Tyser #define FEC_MMFR_ST(x) (((x)&0x03)<<30) 275819833afSPeter Tyser #define FEC_MMFR_ST_01 (0x40000000) 276819833afSPeter Tyser #define FEC_MMFR_OP_RD (0x20000000) 277819833afSPeter Tyser #define FEC_MMFR_OP_WR (0x10000000) 278819833afSPeter Tyser #define FEC_MMFR_PA(x) (((x)&0x1F)<<23) 279819833afSPeter Tyser #define FEC_MMFR_RA(x) (((x)&0x1F)<<18) 280819833afSPeter Tyser #define FEC_MMFR_TA(x) (((x)&0x03)<<16) 281819833afSPeter Tyser #define FEC_MMFR_TA_10 (0x00020000) 282819833afSPeter Tyser 283819833afSPeter Tyser /* Bit definitions and macros for FEC_MSCR */ 284819833afSPeter Tyser #define FEC_MSCR_DIS_PREAMBLE (0x00000080) 285819833afSPeter Tyser #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) 286819833afSPeter Tyser 287819833afSPeter Tyser /* Bit definitions and macros for FEC_MIBC */ 288819833afSPeter Tyser #define FEC_MIBC_MIB_DISABLE (0x80000000) 289819833afSPeter Tyser #define FEC_MIBC_MIB_IDLE (0x40000000) 290819833afSPeter Tyser 291819833afSPeter Tyser /* Bit definitions and macros for FEC_RCR */ 292819833afSPeter Tyser #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) 293819833afSPeter Tyser #define FEC_RCR_FCE (0x00000020) 294819833afSPeter Tyser #define FEC_RCR_BC_REJ (0x00000010) 295819833afSPeter Tyser #define FEC_RCR_PROM (0x00000008) 296819833afSPeter Tyser #define FEC_RCR_MII_MODE (0x00000004) 297819833afSPeter Tyser #define FEC_RCR_DRT (0x00000002) 298819833afSPeter Tyser #define FEC_RCR_LOOP (0x00000001) 299819833afSPeter Tyser 300819833afSPeter Tyser /* Bit definitions and macros for FEC_TCR */ 301819833afSPeter Tyser #define FEC_TCR_RFC_PAUSE (0x00000010) 302819833afSPeter Tyser #define FEC_TCR_TFC_PAUSE (0x00000008) 303819833afSPeter Tyser #define FEC_TCR_FDEN (0x00000004) 304819833afSPeter Tyser #define FEC_TCR_HBC (0x00000002) 305819833afSPeter Tyser #define FEC_TCR_GTS (0x00000001) 306819833afSPeter Tyser 307819833afSPeter Tyser /* Bit definitions and macros for FEC_PAUR */ 308819833afSPeter Tyser #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) 309819833afSPeter Tyser #define FEC_PAUR_TYPE(x) ((x)&0xFFFF) 310819833afSPeter Tyser 311819833afSPeter Tyser /* Bit definitions and macros for FEC_OPD */ 312819833afSPeter Tyser #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) 313819833afSPeter Tyser #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) 314819833afSPeter Tyser 315819833afSPeter Tyser /* Bit definitions and macros for FEC_TFWR */ 316819833afSPeter Tyser #define FEC_TFWR_X_WMRK(x) ((x)&0x03) 317819833afSPeter Tyser #define FEC_TFWR_X_WMRK_64 (0x01) 318819833afSPeter Tyser #define FEC_TFWR_X_WMRK_128 (0x02) 319819833afSPeter Tyser #define FEC_TFWR_X_WMRK_192 (0x03) 320819833afSPeter Tyser 321819833afSPeter Tyser /* Bit definitions and macros for FEC_FRBR */ 322819833afSPeter Tyser #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) 323819833afSPeter Tyser 324819833afSPeter Tyser /* Bit definitions and macros for FEC_FRSR */ 325819833afSPeter Tyser #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) 326819833afSPeter Tyser 327819833afSPeter Tyser /* Bit definitions and macros for FEC_ERDSR */ 328819833afSPeter Tyser #define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) 329819833afSPeter Tyser 330819833afSPeter Tyser /* Bit definitions and macros for FEC_ETDSR */ 331819833afSPeter Tyser #define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) 332819833afSPeter Tyser 333819833afSPeter Tyser /* Bit definitions and macros for FEC_EMRBR */ 334819833afSPeter Tyser #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) 335819833afSPeter Tyser 336819833afSPeter Tyser #define FEC_RESET_DELAY 100 337819833afSPeter Tyser #define FEC_RX_TOUT 100 338819833afSPeter Tyser 339819833afSPeter Tyser int fecpin_setclear(struct eth_device *dev, int setclear); 340819833afSPeter Tyser 341819833afSPeter Tyser #ifdef CONFIG_SYS_DISCOVER_PHY 342819833afSPeter Tyser void __mii_init(void); 343819833afSPeter Tyser uint mii_send(uint mii_cmd); 344819833afSPeter Tyser int mii_discover_phy(struct eth_device *dev); 345dfcc496eSJoe Hershberger int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); 346dfcc496eSJoe Hershberger int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, 347dfcc496eSJoe Hershberger u16 value); 348819833afSPeter Tyser #endif 349819833afSPeter Tyser 350819833afSPeter Tyser #endif /* fec_h */ 351