1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * SSI Internal Memory Map 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef __SSI_H__ 10 #define __SSI_H__ 11 12 typedef struct ssi { 13 u32 tx0; 14 u32 tx1; 15 u32 rx0; 16 u32 rx1; 17 u32 cr; 18 u32 isr; 19 u32 ier; 20 u32 tcr; 21 u32 rcr; 22 u32 ccr; 23 u8 resv0[0x4]; 24 u32 fcsr; 25 u8 resv1[0x8]; 26 u32 acr; 27 u32 acadd; 28 u32 acdat; 29 u32 atag; 30 u32 tmask; 31 u32 rmask; 32 } ssi_t; 33 34 #define SSI_CR_CIS (0x00000200) 35 #define SSI_CR_TCH (0x00000100) 36 #define SSI_CR_MCE (0x00000080) 37 #define SSI_CR_I2S_MASK (0xFFFFFF9F) 38 #define SSI_CR_I2S_SLAVE (0x00000040) 39 #define SSI_CR_I2S_MASTER (0x00000020) 40 #define SSI_CR_I2S_NORMAL (0x00000000) 41 #define SSI_CR_SYN (0x00000010) 42 #define SSI_CR_NET (0x00000008) 43 #define SSI_CR_RE (0x00000004) 44 #define SSI_CR_TE (0x00000002) 45 #define SSI_CR_SSI_EN (0x00000001) 46 47 #define SSI_ISR_CMDAU (0x00040000) 48 #define SSI_ISR_CMDDU (0x00020000) 49 #define SSI_ISR_RXT (0x00010000) 50 #define SSI_ISR_RDR1 (0x00008000) 51 #define SSI_ISR_RDR0 (0x00004000) 52 #define SSI_ISR_TDE1 (0x00002000) 53 #define SSI_ISR_TDE0 (0x00001000) 54 #define SSI_ISR_ROE1 (0x00000800) 55 #define SSI_ISR_ROE0 (0x00000400) 56 #define SSI_ISR_TUE1 (0x00000200) 57 #define SSI_ISR_TUE0 (0x00000100) 58 #define SSI_ISR_TFS (0x00000080) 59 #define SSI_ISR_RFS (0x00000040) 60 #define SSI_ISR_TLS (0x00000020) 61 #define SSI_ISR_RLS (0x00000010) 62 #define SSI_ISR_RFF1 (0x00000008) 63 #define SSI_ISR_RFF0 (0x00000004) 64 #define SSI_ISR_TFE1 (0x00000002) 65 #define SSI_ISR_TFE0 (0x00000001) 66 67 #define SSI_IER_RDMAE (0x00400000) 68 #define SSI_IER_RIE (0x00200000) 69 #define SSI_IER_TDMAE (0x00100000) 70 #define SSI_IER_TIE (0x00080000) 71 #define SSI_IER_CMDAU (0x00040000) 72 #define SSI_IER_CMDU (0x00020000) 73 #define SSI_IER_RXT (0x00010000) 74 #define SSI_IER_RDR1 (0x00008000) 75 #define SSI_IER_RDR0 (0x00004000) 76 #define SSI_IER_TDE1 (0x00002000) 77 #define SSI_IER_TDE0 (0x00001000) 78 #define SSI_IER_ROE1 (0x00000800) 79 #define SSI_IER_ROE0 (0x00000400) 80 #define SSI_IER_TUE1 (0x00000200) 81 #define SSI_IER_TUE0 (0x00000100) 82 #define SSI_IER_TFS (0x00000080) 83 #define SSI_IER_RFS (0x00000040) 84 #define SSI_IER_TLS (0x00000020) 85 #define SSI_IER_RLS (0x00000010) 86 #define SSI_IER_RFF1 (0x00000008) 87 #define SSI_IER_RFF0 (0x00000004) 88 #define SSI_IER_TFE1 (0x00000002) 89 #define SSI_IER_TFE0 (0x00000001) 90 91 #define SSI_TCR_TXBIT0 (0x00000200) 92 #define SSI_TCR_TFEN1 (0x00000100) 93 #define SSI_TCR_TFEN0 (0x00000080) 94 #define SSI_TCR_TFDIR (0x00000040) 95 #define SSI_TCR_TXDIR (0x00000020) 96 #define SSI_TCR_TSHFD (0x00000010) 97 #define SSI_TCR_TSCKP (0x00000008) 98 #define SSI_TCR_TFSI (0x00000004) 99 #define SSI_TCR_TFSL (0x00000002) 100 #define SSI_TCR_TEFS (0x00000001) 101 102 #define SSI_RCR_RXEXT (0x00000400) 103 #define SSI_RCR_RXBIT0 (0x00000200) 104 #define SSI_RCR_RFEN1 (0x00000100) 105 #define SSI_RCR_RFEN0 (0x00000080) 106 #define SSI_RCR_RSHFD (0x00000010) 107 #define SSI_RCR_RSCKP (0x00000008) 108 #define SSI_RCR_RFSI (0x00000004) 109 #define SSI_RCR_RFSL (0x00000002) 110 #define SSI_RCR_REFS (0x00000001) 111 112 #define SSI_CCR_DIV2 (0x00040000) 113 #define SSI_CCR_PSR (0x00020000) 114 #define SSI_CCR_WL(x) (((x) & 0x0F) << 13) 115 #define SSI_CCR_WL_MASK (0xFFFE1FFF) 116 #define SSI_CCR_DC(x) (((x)& 0x1F) << 8) 117 #define SSI_CCR_DC_MASK (0xFFFFE0FF) 118 #define SSI_CCR_PM(x) ((x) & 0xFF) 119 #define SSI_CCR_PM_MASK (0xFFFFFF00) 120 121 #define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28) 122 #define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF) 123 #define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24) 124 #define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF) 125 #define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20) 126 #define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF) 127 #define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16) 128 #define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF) 129 #define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12) 130 #define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF) 131 #define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8) 132 #define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF) 133 #define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4) 134 #define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F) 135 #define SSI_FCSR_TFWM0(x) ((x) & 0x0F) 136 #define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0) 137 138 #define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5) 139 #define SSI_ACR_FRDIV_MASK (0xFFFFF81F) 140 #define SSI_ACR_WR (0x00000010) 141 #define SSI_ACR_RD (0x00000008) 142 #define SSI_ACR_TIF (0x00000004) 143 #define SSI_ACR_FV (0x00000002) 144 #define SSI_ACR_AC97EN (0x00000001) 145 146 #define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF) 147 148 #define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF) 149 150 #define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF) 151 152 #endif /* __SSI_H__ */ 153