1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Pulse Width Modulation Memory Map 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef __ATA_H__ 10 #define __ATA_H__ 11 12 /* Pulse Width Modulation (PWM) */ 13 typedef struct pwm_ctrl { 14 #ifdef CONFIG_M5272 15 u8 cr0; 16 u8 res1[3]; 17 u8 cr1; 18 u8 res2[3]; 19 u8 cr2; 20 u8 res3[7]; 21 u8 pwr0; 22 u8 res4[3]; 23 u8 pwr1; 24 u8 res5[3]; 25 u8 pwr2; 26 u8 res6[7]; 27 #else 28 u8 en; /* 0x00 PWM Enable */ 29 u8 pol; /* 0x01 Polarity */ 30 u8 clk; /* 0x02 Clock Select */ 31 u8 prclk; /* 0x03 Prescale Clock Select */ 32 u8 cae; /* 0x04 Center Align Enable */ 33 u8 ctl; /* 0x05 Control */ 34 u16 res1; /* 0x06 - 0x07 */ 35 u8 scla; /* 0x08 Scale A */ 36 u8 sclb; /* 0x09 Scale B */ 37 u16 res2; /* 0x0A - 0x0B */ 38 #ifdef CONFIG_M5275 39 u8 cnt[4]; /* 0x0C Channel n Counter */ 40 u16 res3; /* 0x10 - 0x11 */ 41 u8 per[4]; /* 0x14 Channel n Period */ 42 u16 res4; /* 0x16 - 0x17 */ 43 u8 dty[4]; /* 0x18 Channel n Duty */ 44 #else 45 u8 cnt[8]; /* 0x0C Channel n Counter */ 46 u8 per[8]; /* 0x14 Channel n Period */ 47 u8 dty[8]; /* 0x1C Channel n Duty */ 48 u8 sdn; /* 0x24 Shutdown */ 49 u8 res3[3]; /* 0x25 - 0x27 */ 50 #endif /* CONFIG_M5275 */ 51 #endif /* CONFIG_M5272 */ 52 } pwm_t; 53 54 #ifdef CONFIG_M5272 55 56 #define PWM_CR_EN (0x80) 57 #define PWM_CR_FRC1 (0x40) 58 #define PWM_CR_LVL (0x20) 59 #define PWM_CR_CLKSEL(x) ((x) & 0x0F) 60 #define PWM_CR_CLKSEL_MASK (0xF0) 61 62 #else 63 64 #define PWM_EN_PWMEn(x) (1 << ((x) & 0x07)) 65 #define PWM_EN_PWMEn_MASK (0xF0) 66 67 #define PWM_POL_PPOLn(x) (1 << ((x) & 0x07)) 68 #define PWM_POL_PPOLn_MASK (0xF0) 69 70 #define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) 71 #define PWM_CLK_PCLKn_MASK (0xF0) 72 73 #define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4) 74 #define PWM_PRCLK_PCKB_MASK (0x8F) 75 #define PWM_PRCLK_PCKA(x) ((x) & 0x07) 76 #define PWM_PRCLK_PCKA_MASK (0xF8) 77 78 #define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) 79 #define PWM_CLK_PCLKn_MASK (0xF0) 80 81 #define PWM_CTL_CON67 (0x80) 82 #define PWM_CTL_CON45 (0x40) 83 #define PWM_CTL_CON23 (0x20) 84 #define PWM_CTL_CON01 (0x10) 85 #define PWM_CTL_PSWAR (0x08) 86 #define PWM_CTL_PFRZ (0x04) 87 88 #define PWM_SDN_IF (0x80) 89 #define PWM_SDN_IE (0x40) 90 #define PWM_SDN_RESTART (0x20) 91 #define PWM_SDN_LVL (0x10) 92 #define PWM_SDN_PWM7IN (0x04) 93 #define PWM_SDN_PWM7IL (0x02) 94 #define PWM_SDN_SDNEN (0x01) 95 96 #endif /* CONFIG_M5272 */ 97 98 #endif /* __ATA_H__ */ 99