1 /*
2  * Edge Port Memory Map
3  *
4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __EPORT_H__
11 #define __EPORT_H__
12 
13 /* Edge Port Module (EPORT) */
14 typedef struct eport {
15 #ifdef CONFIG_MCF547x_8x
16 	u16 par;	/* 0x00 */
17 	u16 res0;	/* 0x02 */
18 	u8 ddr;		/* 0x04 */
19 	u8 ier;		/* 0x05 */
20 	u16 res1;	/* 0x06 */
21 	u8 dr;		/* 0x08 */
22 	u8 pdr;		/* 0x09 */
23 	u16 res2;	/* 0x0A */
24 	u8 fr;		/* 0x0C */
25 	u8 res3[3];	/* 0x0D */
26 #else
27 	u16 par;	/* 0x00 Pin Assignment */
28 	u8 ddr;		/* 0x02 Data Direction */
29 	u8 ier;		/* 0x03 Interrupt Enable */
30 	u8 dr;		/* 0x04 Data */
31 	u8 pdr;		/* 0x05 Pin Data */
32 	u8 fr;		/* 0x06 Flag */
33 	u8 res0;
34 #endif
35 } eport_t;
36 
37 /* EPPAR */
38 #define EPORT_PAR_EPPA1(x)		(((x)&0x0003)<<2)
39 #define EPORT_PAR_EPPA2(x)		(((x)&0x0003)<<4)
40 #define EPORT_PAR_EPPA3(x)		(((x)&0x0003)<<6)
41 #define EPORT_PAR_EPPA4(x)		(((x)&0x0003)<<8)
42 #define EPORT_PAR_EPPA5(x)		(((x)&0x0003)<<10)
43 #define EPORT_PAR_EPPA6(x)		(((x)&0x0003)<<12)
44 #define EPORT_PAR_EPPA7(x)		(((x)&0x0003)<<14)
45 #define EPORT_PAR_LEVEL			(0)
46 #define EPORT_PAR_RISING		(1)
47 #define EPORT_PAR_FALLING		(2)
48 #define EPORT_PAR_BOTH			(3)
49 #define EPORT_PAR_EPPA7_LEVEL		(0x0000)
50 #define EPORT_PAR_EPPA7_RISING		(0x4000)
51 #define EPORT_PAR_EPPA7_FALLING		(0x8000)
52 #define EPORT_PAR_EPPA7_BOTH		(0xC000)
53 #define EPORT_PAR_EPPA6_LEVEL		(0x0000)
54 #define EPORT_PAR_EPPA6_RISING		(0x1000)
55 #define EPORT_PAR_EPPA6_FALLING		(0x2000)
56 #define EPORT_PAR_EPPA6_BOTH		(0x3000)
57 #define EPORT_PAR_EPPA5_LEVEL		(0x0000)
58 #define EPORT_PAR_EPPA5_RISING		(0x0400)
59 #define EPORT_PAR_EPPA5_FALLING		(0x0800)
60 #define EPORT_PAR_EPPA5_BOTH		(0x0C00)
61 #define EPORT_PAR_EPPA4_LEVEL		(0x0000)
62 #define EPORT_PAR_EPPA4_RISING		(0x0100)
63 #define EPORT_PAR_EPPA4_FALLING		(0x0200)
64 #define EPORT_PAR_EPPA4_BOTH		(0x0300)
65 #define EPORT_PAR_EPPA3_LEVEL		(0x0000)
66 #define EPORT_PAR_EPPA3_RISING		(0x0040)
67 #define EPORT_PAR_EPPA3_FALLING		(0x0080)
68 #define EPORT_PAR_EPPA3_BOTH		(0x00C0)
69 #define EPORT_PAR_EPPA2_LEVEL		(0x0000)
70 #define EPORT_PAR_EPPA2_RISING		(0x0010)
71 #define EPORT_PAR_EPPA2_FALLING		(0x0020)
72 #define EPORT_PAR_EPPA2_BOTH		(0x0030)
73 #define EPORT_PAR_EPPA1_LEVEL		(0x0000)
74 #define EPORT_PAR_EPPA1_RISING		(0x0004)
75 #define EPORT_PAR_EPPA1_FALLING		(0x0008)
76 #define EPORT_PAR_EPPA1_BOTH		(0x000C)
77 
78 /* EPDDR */
79 #define EPORT_DDR_EPDD1			(0x02)
80 #define EPORT_DDR_EPDD2			(0x04)
81 #define EPORT_DDR_EPDD3			(0x08)
82 #define EPORT_DDR_EPDD4			(0x10)
83 #define EPORT_DDR_EPDD5			(0x20)
84 #define EPORT_DDR_EPDD6			(0x40)
85 #define EPORT_DDR_EPDD7			(0x80)
86 
87 /* EPIER */
88 #define EPORT_IER_EPIE1			(0x02)
89 #define EPORT_IER_EPIE2			(0x04)
90 #define EPORT_IER_EPIE3			(0x08)
91 #define EPORT_IER_EPIE4			(0x10)
92 #define EPORT_IER_EPIE5			(0x20)
93 #define EPORT_IER_EPIE6			(0x40)
94 #define EPORT_IER_EPIE7			(0x80)
95 
96 /* EPDR */
97 #define EPORT_DR_EPD1			(0x02)
98 #define EPORT_DR_EPD2			(0x04)
99 #define EPORT_DR_EPD3			(0x08)
100 #define EPORT_DR_EPD4			(0x10)
101 #define EPORT_DR_EPD5			(0x20)
102 #define EPORT_DR_EPD6			(0x40)
103 #define EPORT_DR_EPD7			(0x80)
104 
105 /* EPPDR */
106 #define EPORT_PDR_EPPD1			(0x02)
107 #define EPORT_PDR_EPPD2			(0x04)
108 #define EPORT_PDR_EPPD3			(0x08)
109 #define EPORT_PDR_EPPD4			(0x10)
110 #define EPORT_PDR_EPPD5			(0x20)
111 #define EPORT_PDR_EPPD6			(0x40)
112 #define EPORT_PDR_EPPD7			(0x80)
113 
114 /* EPFR */
115 #define EPORT_FR_EPF1			(0x02)
116 #define EPORT_FR_EPF2			(0x04)
117 #define EPORT_FR_EPF3			(0x08)
118 #define EPORT_FR_EPF4			(0x10)
119 #define EPORT_FR_EPF5			(0x20)
120 #define EPORT_FR_EPF6			(0x40)
121 #define EPORT_FR_EPF7			(0x80)
122 
123 #endif				/* __EPORT_H__ */
124