1 /* 2 * ColdFire cache 3 * 4 * Copyright 2004-2012 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CACHE_H 11 #define __CACHE_H 12 13 #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ 14 defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) 15 #define CONFIG_CF_V2 16 #endif 17 18 #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \ 19 defined(CONFIG_MCF5301x) 20 #define CONFIG_CF_V3 21 #endif 22 23 #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) 24 #define CONFIG_CF_V4 25 #elif defined(CONFIG_MCF5441x) 26 #define CONFIG_CF_V4E /* Four Extra ACRn */ 27 #endif 28 29 /* ***** CACR ***** */ 30 /* V2 Core */ 31 #ifdef CONFIG_CF_V2 32 33 #define CF_CACR_CENB (1 << 31) 34 #define CF_CACR_CPD (1 << 28) 35 #define CF_CACR_CFRZ (1 << 27) 36 #define CF_CACR_CEIB (1 << 10) 37 #define CF_CACR_DCM (1 << 9) 38 #define CF_CACR_DBWE (1 << 8) 39 40 #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) 41 #define CF_CACR_DWP (1 << 6) 42 #else 43 #define CF_CACR_CINV (1 << 24) 44 #define CF_CACR_DISI (1 << 23) 45 #define CF_CACR_DISD (1 << 22) 46 #define CF_CACR_INVI (1 << 21) 47 #define CF_CACR_INVD (1 << 20) 48 #define CF_CACR_DWP (1 << 5) 49 #define CF_CACR_EUSP (1 << 4) 50 #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ 51 52 #endif /* CONFIG_CF_V2 */ 53 54 /* V3 Core */ 55 #ifdef CONFIG_CF_V3 56 57 #define CF_CACR_EC (1 << 31) 58 #define CF_CACR_ESB (1 << 29) 59 #define CF_CACR_DPI (1 << 28) 60 #define CF_CACR_HLCK (1 << 27) 61 #define CF_CACR_CINVA (1 << 24) 62 #define CF_CACR_DNFB (1 << 10) 63 #define CF_CACR_DCM_UNMASK 0xFFFFFCFF 64 #define CF_CACR_DCM_WT (0 << 8) 65 #define CF_CACR_DCM_CB (1 << 8) 66 #define CF_CACR_DCM_P (2 << 8) 67 #define CF_CACR_DCM_IP (3 << 8) 68 #define CF_CACR_DW (1 << 5) 69 #define CF_CACR_EUSP (1 << 4) 70 71 #endif /* CONFIG_CF_V3 */ 72 73 /* V4 Core */ 74 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) 75 76 #define CF_CACR_DEC (1 << 31) 77 #define CF_CACR_DW (1 << 30) 78 #define CF_CACR_DESB (1 << 29) 79 #define CF_CACR_DDPI (1 << 28) 80 #define CF_CACR_DHLCK (1 << 27) 81 #define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) 82 #define CF_CACR_DDCM_WT (0 << 25) 83 #define CF_CACR_DDCM_CB (1 << 25) 84 #define CF_CACR_DDCM_P (2 << 25) 85 #define CF_CACR_DDCM_IP (3 << 25) 86 #define CF_CACR_DCINVA (1 << 24) 87 88 #define CF_CACR_DDSP (1 << 23) 89 #define CF_CACR_BEC (1 << 19) 90 #define CF_CACR_BCINVA (1 << 18) 91 #define CF_CACR_IEC (1 << 15) 92 #define CF_CACR_DNFB (1 << 13) 93 #define CF_CACR_IDPI (1 << 12) 94 #define CF_CACR_IHLCK (1 << 11) 95 #define CF_CACR_IDCM (1 << 10) 96 #define CF_CACR_ICINVA (1 << 8) 97 #define CF_CACR_IDSP (1 << 7) 98 #define CF_CACR_EUSP (1 << 5) 99 100 #if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) 101 #define CF_CACR_IVO (1 << 20) 102 #define CF_CACR_SPA (1 << 14) 103 #else 104 #define CF_CACR_DF (1 << 4) 105 #endif 106 107 #endif /* CONFIG_CF_V4 */ 108 109 /* ***** ACR ***** */ 110 #define CF_ACR_ADR_UNMASK (0x00FFFFFF) 111 #define CF_ACR_ADR(x) ((x & 0xFF) << 24) 112 #define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) 113 #define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) 114 #define CF_ACR_EN (1 << 15) 115 #define CF_ACR_SM_UNMASK (0xFFFF9FFF) 116 #define CF_ACR_SM_UM (0 << 13) 117 #define CF_ACR_SM_SM (1 << 13) 118 #define CF_ACR_SM_ALL (3 << 13) 119 #define CF_ACR_WP (1 << 2) 120 121 /* V2 Core */ 122 #ifdef CONFIG_CF_V2 123 #define CF_ACR_CM (1 << 6) 124 #define CF_ACR_BWE (1 << 5) 125 #else 126 /* V3 & V4 */ 127 #define CF_ACR_CM_UNMASK (0xFFFFFF9F) 128 #define CF_ACR_CM_WT (0 << 5) 129 #define CF_ACR_CM_CB (1 << 5) 130 #define CF_ACR_CM_P (2 << 5) 131 #define CF_ACR_CM_IP (3 << 5) 132 #endif /* CONFIG_CF_V2 */ 133 134 /* V4 Core */ 135 #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) 136 #define CF_ACR_AMM (1 << 10) 137 #define CF_ACR_SP (1 << 3) 138 #endif /* CONFIG_CF_V4 */ 139 140 141 #ifndef CONFIG_SYS_CACHE_ICACR 142 #define CONFIG_SYS_CACHE_ICACR 0 143 #endif 144 145 #ifndef CONFIG_SYS_CACHE_DCACR 146 #ifdef CONFIG_SYS_CACHE_ICACR 147 #define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR 148 #else 149 #define CONFIG_SYS_CACHE_DCACR 0 150 #endif 151 #endif 152 153 #ifndef CONFIG_SYS_CACHE_ACR0 154 #define CONFIG_SYS_CACHE_ACR0 0 155 #endif 156 157 #ifndef CONFIG_SYS_CACHE_ACR1 158 #define CONFIG_SYS_CACHE_ACR1 0 159 #endif 160 161 #ifndef CONFIG_SYS_CACHE_ACR2 162 #define CONFIG_SYS_CACHE_ACR2 0 163 #endif 164 165 #ifndef CONFIG_SYS_CACHE_ACR3 166 #define CONFIG_SYS_CACHE_ACR3 0 167 #endif 168 169 #ifndef CONFIG_SYS_CACHE_ACR4 170 #define CONFIG_SYS_CACHE_ACR4 0 171 #endif 172 173 #ifndef CONFIG_SYS_CACHE_ACR5 174 #define CONFIG_SYS_CACHE_ACR5 0 175 #endif 176 177 #ifndef CONFIG_SYS_CACHE_ACR6 178 #define CONFIG_SYS_CACHE_ACR6 0 179 #endif 180 181 #ifndef CONFIG_SYS_CACHE_ACR7 182 #define CONFIG_SYS_CACHE_ACR7 0 183 #endif 184 185 #define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) 186 187 #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 188 189 void icache_invalid(void); 190 void dcache_invalid(void); 191 192 #endif 193 194 /* 195 * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer 196 * alignment unless the board configuration has specified a new value. 197 */ 198 #ifdef CONFIG_SYS_CACHELINE_SIZE 199 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 200 #else 201 #define ARCH_DMA_MINALIGN 16 202 #endif 203 204 #endif /* __CACHE_H */ 205