1 /* 2 * ColdFire cache 3 * 4 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CACHE_H 27 #define __CACHE_H 28 29 #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ 30 defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) 31 #define CONFIG_CF_V2 32 #endif 33 34 #if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) 35 #define CONFIG_CF_V3 36 #endif 37 38 #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) 39 #define CONFIG_CF_V4 40 #if defined(CONFIG_MCF5441x) 41 #define CONFIG_CF_V4E /* Four Extra ACRn */ 42 #endif 43 #endif 44 45 /* ***** CACR ***** */ 46 /* V2 Core */ 47 #ifdef CONFIG_CF_V2 48 49 #define CF_CACR_CENB (1 << 31) 50 #define CF_CACR_CPD (1 << 28) 51 #define CF_CACR_CFRZ (1 << 27) 52 #define CF_CACR_CEIB (1 << 10) 53 #define CF_CACR_DCM (1 << 9) 54 #define CF_CACR_DBWE (1 << 8) 55 56 #if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) 57 #define CF_CACR_DWP (1 << 6) 58 #else 59 #define CF_CACR_CINV (1 << 24) 60 #define CF_CACR_DISI (1 << 23) 61 #define CF_CACR_DISD (1 << 22) 62 #define CF_CACR_INVI (1 << 21) 63 #define CF_CACR_INVD (1 << 20) 64 #define CF_CACR_DWP (1 << 5) 65 #define CF_CACR_EUSP (1 << 4) 66 #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ 67 68 #endif /* CONFIG_CF_V2 */ 69 70 /* V3 Core */ 71 #ifdef CONFIG_CF_V3 72 73 #define CF_CACR_EC (1 << 31) 74 #define CF_CACR_ESB (1 << 29) 75 #define CF_CACR_DPI (1 << 28) 76 #define CF_CACR_HLCK (1 << 27) 77 #define CF_CACR_CINVA (1 << 24) 78 #define CF_CACR_DNFB (1 << 10) 79 #define CF_CACR_DCM_UNMASK 0xFFFFFCFF 80 #define CF_CACR_DCM_WT (0 << 8) 81 #define CF_CACR_DCM_CB (1 << 8) 82 #define CF_CACR_DCM_P (2 << 8) 83 #define CF_CACR_DCM_IP (3 << 8) 84 #define CF_CACR_DW (1 << 5) 85 #define CF_CACR_EUSP (1 << 4) 86 87 #endif /* CONFIG_CF_V3 */ 88 89 /* V4 Core */ 90 #ifdef CONFIG_CF_V4 91 92 #define CF_CACR_DEC (1 << 31) 93 #define CF_CACR_DW (1 << 30) 94 #define CF_CACR_DESB (1 << 29) 95 #define CF_CACR_DDPI (1 << 28) 96 #define CF_CACR_DHLCK (1 << 27) 97 #define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) 98 #define CF_CACR_DDCM_WT (0 << 25) 99 #define CF_CACR_DDCM_CB (1 << 25) 100 #define CF_CACR_DDCM_P (2 << 25) 101 #define CF_CACR_DDCM_IP (3 << 25) 102 #define CF_CACR_DCINVA (1 << 24) 103 104 #define CF_CACR_DDSP (1 << 23) 105 #define CF_CACR_BEC (1 << 19) 106 #define CF_CACR_BCINVA (1 << 18) 107 #define CF_CACR_IEC (1 << 15) 108 #define CF_CACR_DNFB (1 << 13) 109 #define CF_CACR_IDPI (1 << 12) 110 #define CF_CACR_IHLCK (1 << 11) 111 #define CF_CACR_IDCM (1 << 10) 112 #define CF_CACR_ICINVA (1 << 8) 113 #define CF_CACR_IDSP (1 << 7) 114 #define CF_CACR_EUSP (1 << 5) 115 116 #ifdef CONFIG_MCF5445x 117 #define CF_CACR_IVO (1 << 20) 118 #define CF_CACR_SPA (1 << 14) 119 #else 120 #define CF_CACR_DF (1 << 4) 121 #endif 122 123 #endif /* CONFIG_CF_V4 */ 124 125 /* ***** ACR ***** */ 126 #define CF_ACR_ADR_UNMASK (0x00FFFFFF) 127 #define CF_ACR_ADR(x) ((x & 0xFF) << 24) 128 #define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) 129 #define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) 130 #define CF_ACR_EN (1 << 15) 131 #define CF_ACR_SM_UNMASK (0xFFFF9FFF) 132 #define CF_ACR_SM_UM (0 << 13) 133 #define CF_ACR_SM_SM (1 << 13) 134 #define CF_ACR_SM_ALL (3 << 13) 135 #define CF_ACR_WP (1 << 2) 136 137 /* V2 Core */ 138 #ifdef CONFIG_CF_V2 139 #define CF_ACR_CM (1 << 6) 140 #define CF_ACR_BWE (1 << 5) 141 #else 142 /* V3 & V4 */ 143 #define CF_ACR_CM_UNMASK (0xFFFFFF9F) 144 #define CF_ACR_CM_WT (0 << 5) 145 #define CF_ACR_CM_CB (1 << 5) 146 #define CF_ACR_CM_P (2 << 5) 147 #define CF_ACR_CM_IP (3 << 5) 148 #endif /* CONFIG_CF_V2 */ 149 150 /* V4 Core */ 151 #ifdef CONFIG_CF_V4 152 #define CF_ACR_AMM (1 << 10) 153 #define CF_ACR_SP (1 << 3) 154 #endif /* CONFIG_CF_V4 */ 155 156 157 #ifndef CONFIG_SYS_CACHE_ICACR 158 #define CONFIG_SYS_CACHE_ICACR 0 159 #endif 160 161 #ifndef CONFIG_SYS_CACHE_DCACR 162 #ifdef CONFIG_SYS_CACHE_ICACR 163 #define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR 164 #else 165 #define CONFIG_SYS_CACHE_DCACR 0 166 #endif 167 #endif 168 169 #ifndef CONFIG_SYS_CACHE_ACR0 170 #define CONFIG_SYS_CACHE_ACR0 0 171 #endif 172 173 #ifndef CONFIG_SYS_CACHE_ACR1 174 #define CONFIG_SYS_CACHE_ACR1 0 175 #endif 176 177 #ifndef CONFIG_SYS_CACHE_ACR2 178 #define CONFIG_SYS_CACHE_ACR2 0 179 #endif 180 181 #ifndef CONFIG_SYS_CACHE_ACR3 182 #define CONFIG_SYS_CACHE_ACR3 0 183 #endif 184 185 #ifndef CONFIG_SYS_CACHE_ACR4 186 #define CONFIG_SYS_CACHE_ACR4 0 187 #endif 188 189 #ifndef CONFIG_SYS_CACHE_ACR5 190 #define CONFIG_SYS_CACHE_ACR5 0 191 #endif 192 193 #ifndef CONFIG_SYS_CACHE_ACR6 194 #define CONFIG_SYS_CACHE_ACR6 0 195 #endif 196 197 #ifndef CONFIG_SYS_CACHE_ACR7 198 #define CONFIG_SYS_CACHE_ACR7 0 199 #endif 200 201 #define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) 202 203 #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 204 205 void icache_invalid(void); 206 void dcache_invalid(void); 207 208 #endif 209 210 /* 211 * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer 212 * alignment unless the board configuration has specified a new value. 213 */ 214 #ifdef CONFIG_SYS_CACHELINE_SIZE 215 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 216 #else 217 #define ARCH_DMA_MINALIGN 16 218 #endif 219 220 #endif /* __CACHE_H */ 221