1 /* 2 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * PCI Configuration space access support 10 */ 11 #include <common.h> 12 #include <pci.h> 13 #include <asm/io.h> 14 #include <asm/immap.h> 15 16 #if defined(CONFIG_PCI) 17 /* System RAM mapped over PCI */ 18 #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE 19 #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE 20 #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) 21 22 #define cfg_read(val, addr, type, op) *val = op((type)(addr)); 23 #define cfg_write(val, addr, type, op) op((type *)(addr), (val)); 24 25 #define PCI_OP(rw, size, type, op, mask) \ 26 int pci_##rw##_cfg_##size(struct pci_controller *hose, \ 27 pci_dev_t dev, int offset, type val) \ 28 { \ 29 u32 addr = 0; \ 30 u16 cfg_type = 0; \ 31 addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ 32 out_be32(hose->cfg_addr, addr); \ 33 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ 34 __asm__ __volatile__("nop"); \ 35 __asm__ __volatile__("nop"); \ 36 out_be32(hose->cfg_addr, addr & 0x7fffffff); \ 37 return 0; \ 38 } 39 40 PCI_OP(read, byte, u8 *, in_8, 3) 41 PCI_OP(read, word, u16 *, in_le16, 2) 42 PCI_OP(write, byte, u8, out_8, 3) 43 PCI_OP(write, word, u16, out_le16, 2) 44 PCI_OP(write, dword, u32, out_le32, 0) 45 46 int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, 47 int offset, u32 * val) 48 { 49 u32 addr; 50 u32 tmpv; 51 u32 mask = 2; /* word access */ 52 /* Read lower 16 bits */ 53 addr = ((offset & 0xfc) | (dev) | 0x80000000); 54 out_be32(hose->cfg_addr, addr); 55 *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); 56 __asm__ __volatile__("nop"); 57 out_be32(hose->cfg_addr, addr & 0x7fffffff); 58 59 /* Read upper 16 bits */ 60 offset += 2; 61 addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); 62 out_be32(hose->cfg_addr, addr); 63 tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); 64 __asm__ __volatile__("nop"); 65 out_be32(hose->cfg_addr, addr & 0x7fffffff); 66 67 /* combine results into dword value */ 68 *val = (tmpv << 16) | *val; 69 70 return 0; 71 } 72 73 void pci_mcf547x_8x_init(struct pci_controller *hose) 74 { 75 pci_t *pci = (pci_t *) MMAP_PCI; 76 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 77 78 /* Port configuration */ 79 out_be16(&gpio->par_pcibg, 80 GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | 81 GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | 82 GPIO_PAR_PCIBG_PCIBG4(3)); 83 out_be16(&gpio->par_pcibr, 84 GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | 85 GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | 86 GPIO_PAR_PCIBR_PCIBR4(3)); 87 88 /* Assert reset bit */ 89 setbits_be32(&pci->gscr, PCI_GSCR_PR); 90 91 out_be32(&pci->tcr1, PCI_TCR1_P); 92 93 /* Initiator windows */ 94 out_be32(&pci->iw0btar, 95 CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); 96 out_be32(&pci->iw1btar, 97 CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); 98 out_be32(&pci->iw2btar, 99 CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); 100 101 out_be32(&pci->iwcr, 102 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | 103 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); 104 105 out_be32(&pci->icr, 0); 106 107 /* Enable bus master and mem access */ 108 out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); 109 110 /* Cache line size and master latency */ 111 out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8)); 112 out_be32(&pci->cr2, 0); 113 114 #ifdef CONFIG_SYS_PCI_BAR0 115 out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); 116 out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); 117 #endif 118 #ifdef CONFIG_SYS_PCI_BAR1 119 out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); 120 out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); 121 #endif 122 123 /* Deassert reset bit */ 124 clrbits_be32(&pci->gscr, PCI_GSCR_PR); 125 udelay(1000); 126 127 /* Enable PCI bus master support */ 128 hose->first_busno = 0; 129 hose->last_busno = 0xff; 130 131 pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, 132 CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); 133 134 pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, 135 CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); 136 137 pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, 138 CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, 139 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 140 141 hose->region_count = 3; 142 143 hose->cfg_addr = &(pci->car); 144 hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; 145 146 pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, 147 pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, 148 pci_write_cfg_dword); 149 150 /* Hose scan */ 151 pci_register_hose(hose); 152 hose->last_busno = pci_hose_scan(hose); 153 } 154 #endif /* CONFIG_PCI */ 155