1 /* 2 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * PCI Configuration space access support 26 */ 27 #include <common.h> 28 #include <pci.h> 29 #include <asm/io.h> 30 #include <asm/immap.h> 31 32 #if defined(CONFIG_PCI) 33 /* System RAM mapped over PCI */ 34 #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE 35 #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE 36 #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) 37 38 #define cfg_read(val, addr, type, op) *val = op((type)(addr)); 39 #define cfg_write(val, addr, type, op) op((type *)(addr), (val)); 40 41 #define PCI_OP(rw, size, type, op, mask) \ 42 int pci_##rw##_cfg_##size(struct pci_controller *hose, \ 43 pci_dev_t dev, int offset, type val) \ 44 { \ 45 u32 addr = 0; \ 46 u16 cfg_type = 0; \ 47 addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ 48 out_be32(hose->cfg_addr, addr); \ 49 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ 50 __asm__ __volatile__("nop"); \ 51 __asm__ __volatile__("nop"); \ 52 out_be32(hose->cfg_addr, addr & 0x7fffffff); \ 53 return 0; \ 54 } 55 56 PCI_OP(read, byte, u8 *, in_8, 3) 57 PCI_OP(read, word, u16 *, in_le16, 2) 58 PCI_OP(write, byte, u8, out_8, 3) 59 PCI_OP(write, word, u16, out_le16, 2) 60 PCI_OP(write, dword, u32, out_le32, 0) 61 62 int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, 63 int offset, u32 * val) 64 { 65 u32 addr; 66 u32 tmpv; 67 u32 mask = 2; /* word access */ 68 /* Read lower 16 bits */ 69 addr = ((offset & 0xfc) | (dev) | 0x80000000); 70 out_be32(hose->cfg_addr, addr); 71 *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); 72 __asm__ __volatile__("nop"); 73 out_be32(hose->cfg_addr, addr & 0x7fffffff); 74 75 /* Read upper 16 bits */ 76 offset += 2; 77 addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); 78 out_be32(hose->cfg_addr, addr); 79 tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); 80 __asm__ __volatile__("nop"); 81 out_be32(hose->cfg_addr, addr & 0x7fffffff); 82 83 /* combine results into dword value */ 84 *val = (tmpv << 16) | *val; 85 86 return 0; 87 } 88 89 void pci_mcf547x_8x_init(struct pci_controller *hose) 90 { 91 pci_t *pci = (pci_t *) MMAP_PCI; 92 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 93 94 /* Port configuration */ 95 out_be16(&gpio->par_pcibg, 96 GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | 97 GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | 98 GPIO_PAR_PCIBG_PCIBG4(3)); 99 out_be16(&gpio->par_pcibr, 100 GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | 101 GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | 102 GPIO_PAR_PCIBR_PCIBR4(3)); 103 104 /* Assert reset bit */ 105 setbits_be32(&pci->gscr, PCI_GSCR_PR); 106 107 out_be32(&pci->tcr1, PCI_TCR1_P); 108 109 /* Initiator windows */ 110 out_be32(&pci->iw0btar, 111 CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); 112 out_be32(&pci->iw1btar, 113 CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); 114 out_be32(&pci->iw2btar, 115 CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); 116 117 out_be32(&pci->iwcr, 118 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | 119 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); 120 121 out_be32(&pci->icr, 0); 122 123 /* Enable bus master and mem access */ 124 out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); 125 126 /* Cache line size and master latency */ 127 out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8)); 128 out_be32(&pci->cr2, 0); 129 130 #ifdef CONFIG_SYS_PCI_BAR0 131 out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); 132 out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); 133 #endif 134 #ifdef CONFIG_SYS_PCI_BAR1 135 out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); 136 out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); 137 #endif 138 139 /* Deassert reset bit */ 140 clrbits_be32(&pci->gscr, PCI_GSCR_PR); 141 udelay(1000); 142 143 /* Enable PCI bus master support */ 144 hose->first_busno = 0; 145 hose->last_busno = 0xff; 146 147 pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, 148 CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); 149 150 pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, 151 CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); 152 153 pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, 154 CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, 155 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 156 157 hose->region_count = 3; 158 159 hose->cfg_addr = &(pci->car); 160 hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; 161 162 pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, 163 pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, 164 pci_write_cfg_dword); 165 166 /* Hose scan */ 167 pci_register_hose(hose); 168 hose->last_busno = pci_hose_scan(hose); 169 } 170 #endif /* CONFIG_PCI */ 171