1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <MCD_dma.h> 30 #include <asm/immap.h> 31 #include <asm/io.h> 32 33 #if defined(CONFIG_CMD_NET) 34 #include <config.h> 35 #include <net.h> 36 #include <asm/fsl_mcdmafec.h> 37 #endif 38 39 /* 40 * Breath some life into the CPU... 41 * 42 * Set up the memory map, 43 * initialize a bunch of registers, 44 * initialize the UPM's 45 */ 46 void cpu_init_f(void) 47 { 48 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 49 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 50 xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB; 51 52 out_be32(&xlbarb->adrto, 0x2000); 53 out_be32(&xlbarb->datto, 0x2500); 54 out_be32(&xlbarb->busto, 0x3000); 55 56 out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT); 57 58 /* Master Priority Enable */ 59 out_be32(&xlbarb->prien, 0xff); 60 out_be32(&xlbarb->pri, 0); 61 62 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) 63 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 64 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 65 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 66 #endif 67 68 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) 69 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 70 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 71 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 72 #endif 73 74 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) 75 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 76 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 77 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 78 #endif 79 80 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) 81 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 82 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 83 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 84 #endif 85 86 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) 87 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 88 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 89 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 90 #endif 91 92 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) 93 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 94 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 95 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 96 #endif 97 98 #ifdef CONFIG_FSL_I2C 99 out_be16(&gpio->par_feci2cirq, 100 GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA); 101 #endif 102 103 icache_enable(); 104 } 105 106 /* 107 * initialize higher level parts of CPU like timers 108 */ 109 int cpu_init_r(void) 110 { 111 #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) 112 MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), 113 MCD_RELOC_TASKS); 114 #endif 115 return (0); 116 } 117 118 void uart_port_conf(int port) 119 { 120 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 121 u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); 122 123 /* Setup Ports: */ 124 switch (port) { 125 case 0: 126 out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); 127 break; 128 case 1: 129 out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); 130 break; 131 case 2: 132 out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); 133 break; 134 case 3: 135 out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); 136 break; 137 } 138 139 clrbits_8(pscsicr, 0x07); 140 } 141 142 #if defined(CONFIG_CMD_NET) 143 int fecpin_setclear(struct eth_device *dev, int setclear) 144 { 145 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 146 struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; 147 148 if (setclear) { 149 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 150 setbits_be16(&gpio->par_feci2cirq, 0xf000); 151 else 152 setbits_be16(&gpio->par_feci2cirq, 0x0fc0); 153 } else { 154 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 155 clrbits_be16(&gpio->par_feci2cirq, 0xf000); 156 else 157 clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); 158 } 159 return 0; 160 } 161 #endif 162