1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2007 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <MCD_dma.h> 30 #include <asm/immap.h> 31 32 #if defined(CONFIG_CMD_NET) 33 #include <config.h> 34 #include <net.h> 35 #include <asm/fsl_mcdmafec.h> 36 #endif 37 38 /* 39 * Breath some life into the CPU... 40 * 41 * Set up the memory map, 42 * initialize a bunch of registers, 43 * initialize the UPM's 44 */ 45 void cpu_init_f(void) 46 { 47 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 48 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 49 volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; 50 51 xlbarb->adrto = 0x2000; 52 xlbarb->datto = 0x2500; 53 xlbarb->busto = 0x3000; 54 55 xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; 56 57 /* Master Priority Enable */ 58 xlbarb->prien = 0xff; 59 xlbarb->pri = 0; 60 61 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) 62 fbcs->csar0 = CONFIG_SYS_CS0_BASE; 63 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; 64 fbcs->csmr0 = CONFIG_SYS_CS0_MASK; 65 #endif 66 67 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) 68 fbcs->csar1 = CONFIG_SYS_CS1_BASE; 69 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; 70 fbcs->csmr1 = CONFIG_SYS_CS1_MASK; 71 #endif 72 73 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) 74 fbcs->csar2 = CONFIG_SYS_CS2_BASE; 75 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; 76 fbcs->csmr2 = CONFIG_SYS_CS2_MASK; 77 #endif 78 79 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) 80 fbcs->csar3 = CONFIG_SYS_CS3_BASE; 81 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; 82 fbcs->csmr3 = CONFIG_SYS_CS3_MASK; 83 #endif 84 85 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) 86 fbcs->csar4 = CONFIG_SYS_CS4_BASE; 87 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; 88 fbcs->csmr4 = CONFIG_SYS_CS4_MASK; 89 #endif 90 91 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) 92 fbcs->csar5 = CONFIG_SYS_CS5_BASE; 93 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; 94 fbcs->csmr5 = CONFIG_SYS_CS5_MASK; 95 #endif 96 97 #ifdef CONFIG_FSL_I2C 98 gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; 99 #endif 100 101 icache_enable(); 102 } 103 104 /* 105 * initialize higher level parts of CPU like timers 106 */ 107 int cpu_init_r(void) 108 { 109 #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) 110 MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), 111 MCD_RELOC_TASKS); 112 #endif 113 return (0); 114 } 115 116 void uart_port_conf(int port) 117 { 118 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 119 volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); 120 121 /* Setup Ports: */ 122 switch (port) { 123 case 0: 124 gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); 125 break; 126 case 1: 127 gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); 128 break; 129 case 2: 130 gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); 131 break; 132 case 3: 133 gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); 134 break; 135 } 136 137 *pscsicr &= 0xF8; 138 } 139 140 #if defined(CONFIG_CMD_NET) 141 int fecpin_setclear(struct eth_device *dev, int setclear) 142 { 143 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 144 struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; 145 146 if (setclear) { 147 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 148 gpio->par_feci2cirq |= 0xF000; 149 else 150 gpio->par_feci2cirq |= 0x0FC0; 151 } else { 152 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 153 gpio->par_feci2cirq &= 0x0FFF; 154 else 155 gpio->par_feci2cirq &= 0xF03F; 156 } 157 return 0; 158 } 159 #endif 160