1/* 2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> 3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> 4 * 5 * Copyright 2010-2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#include <common.h> 12#include <asm-offsets.h> 13#include <config.h> 14#include <timestamp.h> 15#include "version.h" 16#include <asm/cache.h> 17 18#define _START _start 19#define _FAULT _fault 20 21#define SAVE_ALL \ 22 move.w #0x2700,%sr; /* disable intrs */ \ 23 subl #60,%sp; /* space for 15 regs */ \ 24 moveml %d0-%d7/%a0-%a6,%sp@; 25 26#define RESTORE_ALL \ 27 moveml %sp@,%d0-%d7/%a0-%a6; \ 28 addl #60,%sp; /* space for 15 regs */ \ 29 rte; 30 31#if defined(CONFIG_SERIAL_BOOT) 32#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \ 33 CONFIG_SYS_INIT_RAM_ADDR) 34#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE) 35#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \ 36 CONFIG_SYS_INIT_RAM_ADDR) 37#endif 38 39.text 40 41/* 42 * Vector table. This is used for initial platform startup. 43 * These vectors are to catch any un-intended traps. 44 */ 45_vectors: 46#if defined(CONFIG_SERIAL_BOOT) 47 48INITSP: .long 0 /* Initial SP */ 49#ifdef CONFIG_CF_SBF 50INITPC: .long ASM_DRAMINIT /* Initial PC */ 51#endif 52#ifdef CONFIG_SYS_NAND_BOOT 53INITPC: .long ASM_DRAMINIT_N /* Initial PC */ 54#endif 55 56#else 57 58INITSP: .long 0 /* Initial SP */ 59INITPC: .long _START /* Initial PC */ 60 61#endif 62 63vector02_0F: 64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 66 67/* Reserved */ 68vector10_17: 69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 70 71vector18_1F: 72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 73 74#if !defined(CONFIG_SERIAL_BOOT) 75 76/* TRAP #0 - #15 */ 77vector20_2F: 78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 80 81/* Reserved */ 82vector30_3F: 83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 85 86vector64_127: 87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 95 96vector128_191: 97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 105 106vector192_255: 107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 115#endif 116 117#if defined(CONFIG_SERIAL_BOOT) 118 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ 119asm_sbf_img_hdr: 120 .long 0x00000000 /* checksum, not yet implemented */ 121 .long 0x00040000 /* image length */ 122 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */ 123 124asm_dram_init: 125 move.w #0x2700,%sr /* Mask off Interrupt */ 126 127#ifdef CONFIG_SYS_NAND_BOOT 128 /* for assembly stack */ 129 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 130 movec %d0, %RAMBAR1 131 132 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp 133 clr.l %sp@- 134#endif 135 136#ifdef CONFIG_CF_SBF 137 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 138 movec %d0, %VBR 139 140 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 141 movec %d0, %RAMBAR1 142 143 /* initialize general use internal ram */ 144 move.l #0, %d0 145 move.l #(ICACHE_STATUS), %a1 /* icache */ 146 move.l #(DCACHE_STATUS), %a2 /* dcache */ 147 move.l %d0, (%a1) 148 move.l %d0, (%a2) 149 150 /* invalidate and disable cache */ 151 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 152 movec %d0, %CACR /* Invalidate cache */ 153 move.l #0, %d0 154 movec %d0, %ACR0 155 movec %d0, %ACR1 156 movec %d0, %ACR2 157 movec %d0, %ACR3 158 159 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp 160 clr.l %sp@- 161 162 /* Must disable global address */ 163 move.l #0xFC008000, %a1 164 move.l #(CONFIG_SYS_CS0_BASE), (%a1) 165 move.l #0xFC008008, %a1 166 move.l #(CONFIG_SYS_CS0_CTRL), (%a1) 167 move.l #0xFC008004, %a1 168 move.l #(CONFIG_SYS_CS0_MASK), (%a1) 169#endif /* CONFIG_CF_SBF */ 170 171#ifdef CONFIG_MCF5441x 172 /* TC: enable all peripherals, 173 in the future only enable certain peripherals */ 174 move.l #0xFC04002D, %a1 175 176#if defined(CONFIG_CF_SBF) 177 move.b #23, (%a1) /* dspi */ 178#endif 179 move.b #46, (%a1) /* DDR */ 180 181 /* slew settings */ 182 move.l #0xEC094060, %a1 183 move.b #0, (%a1) 184 185 /* use vco instead of cpu*2 clock for ddr clock */ 186 move.l #0xEC09001A, %a1 187 move.w #0xE01D, (%a1) 188 189 /* DDR settings */ 190 move.l #0xFC0B8180, %a1 191 move.l #0x00000000, (%a1) 192 move.l #0x40000000, (%a1) 193 194 move.l #0xFC0B81AC, %a1 195 move.l #0x01030203, (%a1) 196 197 move.l #0xFC0B8000, %a1 198 move.l #0x01010101, (%a1)+ /* 0x00 */ 199 move.l #0x00000101, (%a1)+ /* 0x04 */ 200 move.l #0x01010100, (%a1)+ /* 0x08 */ 201 move.l #0x01010000, (%a1)+ /* 0x0C */ 202 move.l #0x00010101, (%a1)+ /* 0x10 */ 203 move.l #0xFC0B8018, %a1 204 move.l #0x00010100, (%a1)+ /* 0x18 */ 205 move.l #0x00000001, (%a1)+ /* 0x1C */ 206 move.l #0x01000001, (%a1)+ /* 0x20 */ 207 move.l #0x00000100, (%a1)+ /* 0x24 */ 208 move.l #0x00010001, (%a1)+ /* 0x28 */ 209 move.l #0x00000200, (%a1)+ /* 0x2C */ 210 move.l #0x01000002, (%a1)+ /* 0x30 */ 211 move.l #0x00000000, (%a1)+ /* 0x34 */ 212 move.l #0x00000100, (%a1)+ /* 0x38 */ 213 move.l #0x02000100, (%a1)+ /* 0x3C */ 214 move.l #0x02000407, (%a1)+ /* 0x40 */ 215 move.l #0x02030007, (%a1)+ /* 0x44 */ 216 move.l #0x02000100, (%a1)+ /* 0x48 */ 217 move.l #0x0A030203, (%a1)+ /* 0x4C */ 218 move.l #0x00020708, (%a1)+ /* 0x50 */ 219 move.l #0x00050008, (%a1)+ /* 0x54 */ 220 move.l #0x04030002, (%a1)+ /* 0x58 */ 221 move.l #0x00000004, (%a1)+ /* 0x5C */ 222 move.l #0x020A0000, (%a1)+ /* 0x60 */ 223 move.l #0x0C00000E, (%a1)+ /* 0x64 */ 224 move.l #0x00002004, (%a1)+ /* 0x68 */ 225 move.l #0x00000000, (%a1)+ /* 0x6C */ 226 move.l #0x00100010, (%a1)+ /* 0x70 */ 227 move.l #0x00100010, (%a1)+ /* 0x74 */ 228 move.l #0x00000000, (%a1)+ /* 0x78 */ 229 move.l #0x07990000, (%a1)+ /* 0x7C */ 230 move.l #0xFC0B80A0, %a1 231 move.l #0x00000000, (%a1)+ /* 0xA0 */ 232 move.l #0x00C80064, (%a1)+ /* 0xA4 */ 233 move.l #0x44520002, (%a1)+ /* 0xA8 */ 234 move.l #0x00C80023, (%a1)+ /* 0xAC */ 235 move.l #0xFC0B80B4, %a1 236 move.l #0x0000C350, (%a1) /* 0xB4 */ 237 move.l #0xFC0B80E0, %a1 238 move.l #0x04000000, (%a1)+ /* 0xE0 */ 239 move.l #0x03000304, (%a1)+ /* 0xE4 */ 240 move.l #0x40040000, (%a1)+ /* 0xE8 */ 241 move.l #0xC0004004, (%a1)+ /* 0xEC */ 242 move.l #0x0642C000, (%a1)+ /* 0xF0 */ 243 move.l #0x00000642, (%a1)+ /* 0xF4 */ 244 move.l #0xFC0B8024, %a1 245 tpf 246 move.l #0x01000100, (%a1) /* 0x24 */ 247 248 move.l #0x2000, %d1 249 jsr asm_delay 250#endif /* CONFIG_MCF5441x */ 251 252#ifdef CONFIG_MCF5445x 253 /* Dram Initialization a1, a2, and d0 */ 254 /* mscr sdram */ 255 move.l #0xFC0A4074, %a1 256 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) 257 nop 258 259 /* SDRAM Chip 0 and 1 */ 260 move.l #0xFC0B8110, %a1 261 move.l #0xFC0B8114, %a2 262 263 /* calculate the size */ 264 move.l #0x13, %d1 265 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 266#ifdef CONFIG_SYS_SDRAM_BASE1 267 lsr.l #1, %d2 268#endif 269 270dramsz_loop: 271 lsr.l #1, %d2 272 add.l #1, %d1 273 cmp.l #1, %d2 274 bne dramsz_loop 275#ifdef CONFIG_SYS_NAND_BOOT 276 beq asm_nand_chk_status 277#endif 278 /* SDRAM Chip 0 and 1 */ 279 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) 280 or.l %d1, (%a1) 281#ifdef CONFIG_SYS_SDRAM_BASE1 282 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) 283 or.l %d1, (%a2) 284#endif 285 nop 286 287 /* dram cfg1 and cfg2 */ 288 move.l #0xFC0B8008, %a1 289 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) 290 nop 291 move.l #0xFC0B800C, %a2 292 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) 293 nop 294 295 move.l #0xFC0B8000, %a1 /* Mode */ 296 move.l #0xFC0B8004, %a2 /* Ctrl */ 297 298 /* Issue PALL */ 299 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) 300 nop 301 302#ifdef CONFIG_M54455EVB 303 /* Issue LEMR */ 304 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) 305 nop 306 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) 307 nop 308#endif 309 310 move.l #1000, %d1 311 jsr asm_delay 312 313 /* Issue PALL */ 314 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) 315 nop 316 317 /* Perform two refresh cycles */ 318 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 319 nop 320 move.l %d0, (%a2) 321 move.l %d0, (%a2) 322 nop 323 324#ifdef CONFIG_M54455EVB 325 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) 326 nop 327#elif defined(CONFIG_M54451EVB) 328 /* Issue LEMR */ 329 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) 330 nop 331 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) 332#endif 333 334 move.l #500, %d1 335 jsr asm_delay 336 337 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 338 and.l #0x7FFFFFFF, %d1 339#ifdef CONFIG_M54455EVB 340 or.l #0x10000C00, %d1 341#elif defined(CONFIG_M54451EVB) 342 or.l #0x10000C00, %d1 343#endif 344 move.l %d1, (%a2) 345 nop 346 347 move.l #2000, %d1 348 jsr asm_delay 349#endif /* CONFIG_MCF5445x */ 350 351#ifdef CONFIG_CF_SBF 352 /* 353 * DSPI Initialization 354 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h 355 * a1 - dspi status 356 * a2 - dtfr 357 * a3 - drfr 358 * a4 - Dst addr 359 */ 360 /* Enable pins for DSPI mode - chip-selects are enabled later */ 361asm_dspi_init: 362#ifdef CONFIG_MCF5441x 363 move.l #0xEC09404E, %a1 364 move.l #0xEC09404F, %a2 365 move.b #0xFF, (%a1) 366 move.b #0x80, (%a2) 367#endif 368 369#ifdef CONFIG_MCF5445x 370 move.l #0xFC0A4063, %a0 371 move.b #0x7F, (%a0) 372#endif 373 /* Configure DSPI module */ 374 move.l #0xFC05C000, %a0 375 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ 376 377 move.l #0xFC05C00C, %a0 378#ifdef CONFIG_MCF5441x 379 move.l #0x3E000016, (%a0) 380#endif 381#ifdef CONFIG_MCF5445x 382 move.l #0x3E000011, (%a0) 383#endif 384 385 move.l #0xFC05C034, %a2 /* dtfr */ 386 move.l #0xFC05C03B, %a3 /* drfr */ 387 388 move.l #(ASM_SBF_IMG_HDR + 4), %a1 389 move.l (%a1)+, %d5 390 move.l (%a1), %a4 391 392 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 393 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 394 395 move.l #0xFC05C02C, %a1 /* dspi status */ 396 397 /* Issue commands and address */ 398 move.l #0x8002000B, %d2 /* Fast Read Cmd */ 399 jsr asm_dspi_wr_status 400 jsr asm_dspi_rd_status 401 402 move.l #0x80020000, %d2 /* Address byte 2 */ 403 jsr asm_dspi_wr_status 404 jsr asm_dspi_rd_status 405 406 move.l #0x80020000, %d2 /* Address byte 1 */ 407 jsr asm_dspi_wr_status 408 jsr asm_dspi_rd_status 409 410 move.l #0x80020000, %d2 /* Address byte 0 */ 411 jsr asm_dspi_wr_status 412 jsr asm_dspi_rd_status 413 414 move.l #0x80020000, %d2 /* Dummy Wr and Rd */ 415 jsr asm_dspi_wr_status 416 jsr asm_dspi_rd_status 417 418 /* Transfer serial boot header to sram */ 419asm_dspi_rd_loop1: 420 move.l #0x80020000, %d2 421 jsr asm_dspi_wr_status 422 jsr asm_dspi_rd_status 423 424 move.b %d1, (%a0) /* read, copy to dst */ 425 426 add.l #1, %a0 /* inc dst by 1 */ 427 sub.l #1, %d4 /* dec cnt by 1 */ 428 bne asm_dspi_rd_loop1 429 430 /* Transfer u-boot from serial flash to memory */ 431asm_dspi_rd_loop2: 432 move.l #0x80020000, %d2 433 jsr asm_dspi_wr_status 434 jsr asm_dspi_rd_status 435 436 move.b %d1, (%a4) /* read, copy to dst */ 437 438 add.l #1, %a4 /* inc dst by 1 */ 439 sub.l #1, %d5 /* dec cnt by 1 */ 440 bne asm_dspi_rd_loop2 441 442 move.l #0x00020000, %d2 /* Terminate */ 443 jsr asm_dspi_wr_status 444 jsr asm_dspi_rd_status 445 446 /* jump to memory and execute */ 447 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0 448 jmp (%a0) 449 450asm_dspi_wr_status: 451 move.l (%a1), %d0 /* status */ 452 and.l #0x0000F000, %d0 453 cmp.l #0x00003000, %d0 454 bgt asm_dspi_wr_status 455 456 move.l %d2, (%a2) 457 rts 458 459asm_dspi_rd_status: 460 move.l (%a1), %d0 /* status */ 461 and.l #0x000000F0, %d0 462 lsr.l #4, %d0 463 cmp.l #0, %d0 464 beq asm_dspi_rd_status 465 466 move.b (%a3), %d1 467 rts 468#endif /* CONFIG_CF_SBF */ 469 470#ifdef CONFIG_SYS_NAND_BOOT 471 /* copy 4 boot pages to dram as soon as possible */ 472 /* each page is 996 bytes (1056 total with 60 ECC bytes */ 473 move.l #0x00000000, %a1 /* src */ 474 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */ 475 move.l #0x3E0, %d0 /* sz in long */ 476 477asm_boot_nand_copy: 478 move.l (%a1)+, (%a2)+ 479 subq.l #1, %d0 480 bne asm_boot_nand_copy 481 482 /* jump to memory and execute */ 483 move.l #(asm_nand_init), %a0 484 jmp (%a0) 485 486asm_nand_init: 487 /* exit nand boot-mode */ 488 move.l #0xFC0FFF30, %a1 489 or.l #0x00000040, %d1 490 move.l %d1, (%a1) 491 492 /* initialize general use internal ram */ 493 move.l #0, %d0 494 move.l #(CACR_STATUS), %a1 /* CACR */ 495 move.l #(ICACHE_STATUS), %a2 /* icache */ 496 move.l #(DCACHE_STATUS), %a3 /* dcache */ 497 move.l %d0, (%a1) 498 move.l %d0, (%a2) 499 move.l %d0, (%a3) 500 501 /* invalidate and disable cache */ 502 move.l #0x01004100, %d0 /* Invalidate cache cmd */ 503 movec %d0, %CACR /* Invalidate cache */ 504 move.l #0, %d0 505 movec %d0, %ACR0 506 movec %d0, %ACR1 507 movec %d0, %ACR2 508 movec %d0, %ACR3 509 510 /* Must disable global address */ 511 move.l #0xFC008000, %a1 512 move.l #(CONFIG_SYS_CS0_BASE), (%a1) 513 move.l #0xFC008008, %a1 514 move.l #(CONFIG_SYS_CS0_CTRL), (%a1) 515 move.l #0xFC008004, %a1 516 move.l #(CONFIG_SYS_CS0_MASK), (%a1) 517 518 /* NAND port configuration */ 519 move.l #0xEC094048, %a1 520 move.b #0xFD, (%a1)+ 521 move.b #0x5F, (%a1)+ 522 move.b #0x04, (%a1)+ 523 524 /* reset nand */ 525 move.l #0xFC0FFF38, %a1 /* isr */ 526 move.l #0x000e0000, (%a1) 527 move.l #0xFC0FFF08, %a2 528 move.l #0x00000000, (%a2)+ /* car */ 529 move.l #0x11000000, (%a2)+ /* rar */ 530 move.l #0x00000000, (%a2)+ /* rpt */ 531 move.l #0x00000000, (%a2)+ /* rai */ 532 move.l #0xFC0FFF2c, %a2 /* cfg */ 533 move.l #0x00000000, (%a2)+ /* secsz */ 534 move.l #0x000e0681, (%a2)+ 535 move.l #0xFC0FFF04, %a2 /* cmd2 */ 536 move.l #0xFF404001, (%a2) 537 move.l #0x000e0000, (%a1) 538 539 move.l #0x2000, %d1 540 jsr asm_delay 541 542 /* setup nand */ 543 move.l #0xFC0FFF00, %a1 544 move.l #0x30700000, (%a1)+ /* cmd1 */ 545 move.l #0x007EF000, (%a1)+ /* cmd2 */ 546 547 move.l #0xFC0FFF2C, %a1 548 move.l #0x00000841, (%a1)+ /* secsz */ 549 move.l #0x000e0681, (%a1)+ /* cfg */ 550 551 move.l #100, %d4 /* 100 pages ~200KB */ 552 move.l #4, %d2 /* start at 4 */ 553 move.l #0xFC0FFF04, %a0 /* cmd2 */ 554 move.l #0xFC0FFF0C, %a1 /* rar */ 555 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2 556 557asm_nand_read: 558 move.l #0x11000000, %d0 /* rar */ 559 or.l %d2, %d0 560 move.l %d0, (%a1) 561 add.l #1, %d2 562 563 move.l (%a0), %d0 /* cmd2 */ 564 or.l #1, %d0 565 move.l %d0, (%a0) 566 567 move.l #0x200, %d1 568 jsr asm_delay 569 570asm_nand_chk_status: 571 move.l #0xFC0FFF38, %a4 /* isr */ 572 move.l (%a4), %d0 573 and.l #0x40000000, %d0 574 tst.l %d0 575 beq asm_nand_chk_status 576 577 move.l #0xFC0FFF38, %a4 /* isr */ 578 move.l (%a4), %d0 579 or.l #0x000E0000, %d0 580 move.l %d0, (%a4) 581 582 move.l #0x200, %d3 583 move.l #0xFC0FC000, %a3 /* buf 1 */ 584asm_nand_copy: 585 move.l (%a3)+, (%a2)+ 586 subq.l #1, %d3 587 bgt asm_nand_copy 588 589 subq.l #1, %d4 590 bgt asm_nand_read 591 592 /* jump to memory and execute */ 593 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0 594 jmp (%a0) 595 596#endif /* CONFIG_SYS_NAND_BOOT */ 597 598asm_delay: 599 nop 600 subq.l #1, %d1 601 bne asm_delay 602 rts 603#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */ 604 605.text 606 . = 0x400 607.globl _start 608_start: 609#if !defined(CONFIG_SERIAL_BOOT) 610 nop 611 nop 612 move.w #0x2700,%sr /* Mask off Interrupt */ 613 614 /* Set vector base register at the beginning of the Flash */ 615 move.l #CONFIG_SYS_FLASH_BASE, %d0 616 movec %d0, %VBR 617 618 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 619 movec %d0, %RAMBAR1 620 621 /* initialize general use internal ram */ 622 move.l #0, %d0 623 move.l #(ICACHE_STATUS), %a1 /* icache */ 624 move.l #(DCACHE_STATUS), %a2 /* dcache */ 625 move.l %d0, (%a1) 626 move.l %d0, (%a2) 627 628 /* invalidate and disable cache */ 629 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 630 movec %d0, %CACR /* Invalidate cache */ 631 move.l #0, %d0 632 movec %d0, %ACR0 633 movec %d0, %ACR1 634 movec %d0, %ACR2 635 movec %d0, %ACR3 636#else 637 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 638 movec %d0, %RAMBAR1 639#endif 640 641 /* put relocation table address to a5 */ 642 move.l #__got_start, %a5 643 644 /* setup stack initially on top of internal static ram */ 645 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp 646 647 /* 648 * if configured, malloc_f arena will be reserved first, 649 * then (and always) gd struct space will be reserved 650 */ 651 move.l %sp, -(%sp) 652 move.l #board_init_f_alloc_reserve, %a1 653 jsr (%a1) 654 655 /* update stack and frame-pointers */ 656 move.l %d0, %sp 657 move.l %sp, %fp 658 659 /* initialize reserved area */ 660 move.l %d0, -(%sp) 661 move.l #board_init_f_init_reserve, %a1 662 jsr (%a1) 663 664 /* run low-level CPU init code (from flash) */ 665 move.l #cpu_init_f, %a1 666 jsr (%a1) 667 668 /* run low-level board init code (from flash) */ 669 clr.l %sp@- 670 move.l #board_init_f, %a1 671 jsr (%a1) 672 673 /* board_init_f() does not return */ 674 675/******************************************************************************/ 676 677/* 678 * void relocate_code (addr_sp, gd, addr_moni) 679 * 680 * This "function" does not return, instead it continues in RAM 681 * after relocating the monitor code. 682 * 683 * r3 = dest 684 * r4 = src 685 * r5 = length in bytes 686 * r6 = cachelinesize 687 */ 688.globl relocate_code 689relocate_code: 690 link.w %a6,#0 691 move.l 8(%a6), %sp /* set new stack pointer */ 692 693 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ 694 move.l 16(%a6), %a0 /* Save copy of Destination Address */ 695 696 move.l #CONFIG_SYS_MONITOR_BASE, %a1 697 move.l #__init_end, %a2 698 move.l %a0, %a3 699 700 /* copy the code to RAM */ 7011: 702 move.l (%a1)+, (%a3)+ 703 cmp.l %a1,%a2 704 bgt.s 1b 705 706/* 707 * We are done. Do not return, instead branch to second part of board 708 * initialization, now running from RAM. 709 */ 710 move.l %a0, %a1 711 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 712 jmp (%a1) 713 714in_ram: 715 716clear_bss: 717 /* 718 * Now clear BSS segment 719 */ 720 move.l %a0, %a1 721 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 722 move.l %a0, %d1 723 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 7246: 725 clr.l (%a1)+ 726 cmp.l %a1,%d1 727 bgt.s 6b 728 729 /* 730 * fix got table in RAM 731 */ 732 move.l %a0, %a1 733 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 734 move.l %a1,%a5 /* fix got pointer register a5 */ 735 736 move.l %a0, %a2 737 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 738 7397: 740 move.l (%a1),%d1 741 sub.l #_start,%d1 742 add.l %a0,%d1 743 move.l %d1,(%a1)+ 744 cmp.l %a2, %a1 745 bne 7b 746 747 /* calculate relative jump to board_init_r in ram */ 748 move.l %a0, %a1 749 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 750 751 /* set parameters for board_init_r */ 752 move.l %a0,-(%sp) /* dest_addr */ 753 move.l %d0,-(%sp) /* gd */ 754 jsr (%a1) 755 756/******************************************************************************/ 757 758/* exception code */ 759.globl _fault 760_fault: 761 bra _fault 762 763.globl _exc_handler 764_exc_handler: 765 SAVE_ALL 766 movel %sp,%sp@- 767 bsr exc_handler 768 addql #4,%sp 769 RESTORE_ALL 770 771.globl _int_handler 772_int_handler: 773 SAVE_ALL 774 movel %sp,%sp@- 775 bsr int_handler 776 addql #4,%sp 777 RESTORE_ALL 778 779/******************************************************************************/ 780 781.globl version_string 782version_string: 783.ascii U_BOOT_VERSION_STRING, "\0" 784.align 4 785