xref: /openbmc/u-boot/arch/m68k/cpu/mcf5445x/start.S (revision 25ddd1fb) 
1/*
2 * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <asm-offsets.h>
25#include <config.h>
26#include <timestamp.h>
27#include "version.h"
28#include <asm/cache.h>
29
30#ifndef	 CONFIG_IDENT_STRING
31#define	 CONFIG_IDENT_STRING ""
32#endif
33
34#define _START	_start
35#define _FAULT	_fault
36
37#define SAVE_ALL						\
38	move.w	#0x2700,%sr;		/* disable intrs */	\
39	subl	#60,%sp;		/* space for 15 regs */ \
40	moveml	%d0-%d7/%a0-%a6,%sp@;
41
42#define RESTORE_ALL						\
43	moveml	%sp@,%d0-%d7/%a0-%a6;				\
44	addl	#60,%sp;		/* space for 15 regs */ \
45	rte;
46
47#if defined(CONFIG_CF_SBF)
48#define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
49#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
50#endif
51
52.text
53
54/*
55 *	Vector table. This is used for initial platform startup.
56 *	These vectors are to catch any un-intended traps.
57 */
58_vectors:
59#if defined(CONFIG_CF_SBF)
60
61INITSP:	.long	0		/* Initial SP	*/
62INITPC:	.long	ASM_DRAMINIT	/* Initial PC 	*/
63
64#else
65
66INITSP:		.long	0	/* Initial SP	*/
67INITPC:		.long	_START	/* Initial PC 		*/
68
69#endif
70
71vector02:	.long	_FAULT	/* Access Error		*/
72vector03:	.long	_FAULT	/* Address Error	*/
73vector04:	.long	_FAULT	/* Illegal Instruction	*/
74vector05:	.long	_FAULT	/* Reserved		*/
75vector06:	.long	_FAULT	/* Reserved		*/
76vector07:	.long	_FAULT	/* Reserved		*/
77vector08:	.long	_FAULT	/* Privilege Violation	*/
78vector09:	.long	_FAULT	/* Trace		*/
79vector0A:	.long	_FAULT	/* Unimplemented A-Line	*/
80vector0B:	.long	_FAULT	/* Unimplemented F-Line	*/
81vector0C:	.long	_FAULT	/* Debug Interrupt	*/
82vector0D:	.long	_FAULT	/* Reserved		*/
83vector0E:	.long	_FAULT	/* Format Error		*/
84vector0F:	.long	_FAULT	/* Unitialized Int.	*/
85
86/* Reserved */
87vector10_17:
88.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89
90vector18:	.long	_FAULT	/* Spurious Interrupt	*/
91vector19:	.long	_FAULT	/* Autovector Level 1	*/
92vector1A:	.long	_FAULT	/* Autovector Level 2	*/
93vector1B:	.long	_FAULT	/* Autovector Level 3	*/
94vector1C:	.long	_FAULT	/* Autovector Level 4	*/
95vector1D:	.long	_FAULT	/* Autovector Level 5	*/
96vector1E:	.long	_FAULT	/* Autovector Level 6	*/
97vector1F:	.long	_FAULT	/* Autovector Level 7	*/
98
99#if !defined(CONFIG_CF_SBF)
100
101/* TRAP #0 - #15 */
102vector20_2F:
103.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105
106/* Reserved	*/
107vector30_3F:
108.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110
111vector64_127:
112.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120
121vector128_191:
122.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
124.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
125.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130
131vector192_255:
132.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
133.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
134.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
135.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140#endif
141
142#if defined(CONFIG_CF_SBF)
143	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
144asm_sbf_img_hdr:
145	.long	0x00000000	/* checksum, not yet implemented */
146	.long	0x00030000	/* image length */
147	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
148
149asm_dram_init:
150	move.w #0x2700,%sr		/* Mask off Interrupt */
151
152	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
153	movec	%d0, %VBR
154
155	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
156	movec	%d0, %RAMBAR1
157
158	/* initialize general use internal ram */
159	move.l #0, %d0
160	move.l #(ICACHE_STATUS), %a1	/* icache */
161	move.l #(DCACHE_STATUS), %a2	/* dcache */
162	move.l %d0, (%a1)
163	move.l %d0, (%a2)
164
165	/* invalidate and disable cache */
166	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
167	movec	%d0, %CACR		/* Invalidate cache */
168	move.l	#0, %d0
169	movec	%d0, %ACR0
170	movec	%d0, %ACR1
171	movec	%d0, %ACR2
172	movec	%d0, %ACR3
173
174	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
175	clr.l %sp@-
176
177	/* Must disable global address */
178	move.l	#0xFC008000, %a1
179	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
180	move.l	#0xFC008008, %a1
181	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
182	move.l	#0xFC008004, %a1
183	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
184
185	/* Dram Initialization a1, a2, and d0 */
186	/* mscr sdram */
187	move.l	#0xFC0A4074, %a1
188	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
189	nop
190
191	/* SDRAM Chip 0 and 1 */
192	move.l	#0xFC0B8110, %a1
193	move.l	#0xFC0B8114, %a2
194
195	/* calculate the size */
196	move.l	#0x13, %d1
197	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
198#ifdef CONFIG_SYS_SDRAM_BASE1
199	lsr.l	#1, %d2
200#endif
201
202dramsz_loop:
203	lsr.l	#1, %d2
204	add.l	#1, %d1
205	cmp.l	#1, %d2
206	bne	dramsz_loop
207
208	/* SDRAM Chip 0 and 1 */
209	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
210	or.l	%d1, (%a1)
211#ifdef CONFIG_SYS_SDRAM_BASE1
212	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
213	or.l	%d1, (%a2)
214#endif
215	nop
216
217	/* dram cfg1 and cfg2 */
218	move.l	#0xFC0B8008, %a1
219	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
220	nop
221	move.l	#0xFC0B800C, %a2
222	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
223	nop
224
225	move.l	#0xFC0B8000, %a1	/* Mode */
226	move.l	#0xFC0B8004, %a2	/* Ctrl */
227
228	/* Issue PALL */
229	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
230	nop
231
232#ifdef CONFIG_M54455EVB
233	/* Issue LEMR */
234	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
235	nop
236	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
237	nop
238#endif
239
240	move.l	#1000, %d1
241	jsr	asm_delay
242
243	/* Issue PALL */
244	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
245	nop
246
247	/* Perform two refresh cycles */
248	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
249	nop
250	move.l	%d0, (%a2)
251	move.l	%d0, (%a2)
252	nop
253
254#ifdef CONFIG_M54455EVB
255	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
256	nop
257#elif defined(CONFIG_M54451EVB)
258	/* Issue LEMR */
259	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
260	nop
261	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
262#endif
263
264	move.l	#500, %d1
265	jsr	asm_delay
266
267	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
268	and.l	#0x7FFFFFFF, %d1
269#ifdef CONFIG_M54455EVB
270	or.l	#0x10000C00, %d1
271#elif defined(CONFIG_M54451EVB)
272	or.l	#0x10000C00, %d1
273#endif
274	move.l	%d1, (%a2)
275	nop
276
277	move.l	#2000, %d1
278	jsr	asm_delay
279
280	/*
281	 * DSPI Initialization
282	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
283	 * a1 - dspi status
284	 * a2 - dtfr
285	 * a3 - drfr
286	 * a4 - Dst addr
287	 */
288	/* Enable pins for DSPI mode - chip-selects are enabled later */
289asm_dspi_init:
290	move.l	#0xFC0A4063, %a0
291	move.b	#0x7F, (%a0)
292
293	/* Configure DSPI module */
294	move.l	#0xFC05C000, %a0
295	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
296
297	move.l	#0xFC05C00C, %a0
298	move.l	#0x3E000011, (%a0)
299
300	move.l	#0xFC05C034, %a2	/* dtfr */
301	move.l	#0xFC05C03B, %a3	/* drfr */
302
303	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
304	move.l	(%a1)+, %d5
305	move.l	(%a1), %a4
306
307	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
308	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
309
310	move.l	#0xFC05C02C, %a1	/* dspi status */
311
312	/* Issue commands and address */
313	move.l	#0x8002000B, %d2	/* Fast Read Cmd */
314	jsr	asm_dspi_wr_status
315	jsr	asm_dspi_rd_status
316
317	move.l	#0x80020000, %d2	/* Address byte 2 */
318	jsr	asm_dspi_wr_status
319	jsr	asm_dspi_rd_status
320
321	move.l	#0x80020000, %d2	/* Address byte 1 */
322	jsr	asm_dspi_wr_status
323	jsr	asm_dspi_rd_status
324
325	move.l	#0x80020000, %d2	/* Address byte 0 */
326	jsr	asm_dspi_wr_status
327	jsr	asm_dspi_rd_status
328
329	move.l	#0x80020000, %d2	/* Dummy Wr and Rd */
330	jsr	asm_dspi_wr_status
331	jsr	asm_dspi_rd_status
332
333	/* Transfer serial boot header to sram */
334asm_dspi_rd_loop1:
335	move.l	#0x80020000, %d2
336	jsr	asm_dspi_wr_status
337	jsr	asm_dspi_rd_status
338
339	move.b	%d1, (%a0)		/* read, copy to dst */
340
341	add.l	#1, %a0			/* inc dst by 1 */
342	sub.l	#1, %d4			/* dec cnt by 1 */
343	bne	asm_dspi_rd_loop1
344
345	/* Transfer u-boot from serial flash to memory */
346asm_dspi_rd_loop2:
347	move.l	#0x80020000, %d2
348	jsr	asm_dspi_wr_status
349	jsr	asm_dspi_rd_status
350
351	move.b	%d1, (%a4)		/* read, copy to dst */
352
353	add.l	#1, %a4			/* inc dst by 1 */
354	sub.l	#1, %d5			/* dec cnt by 1 */
355	bne	asm_dspi_rd_loop2
356
357	move.l	#0x00020000, %d2	/* Terminate */
358	jsr	asm_dspi_wr_status
359	jsr	asm_dspi_rd_status
360
361	/* jump to memory and execute */
362	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
363	jmp	(%a0)
364
365asm_dspi_wr_status:
366	move.l	(%a1), %d0		/* status */
367	and.l	#0x0000F000, %d0
368	cmp.l	#0x00003000, %d0
369	bgt	asm_dspi_wr_status
370
371	move.l	%d2, (%a2)
372	rts
373
374asm_dspi_rd_status:
375	move.l	(%a1), %d0		/* status */
376	and.l	#0x000000F0, %d0
377	lsr.l	#4, %d0
378	cmp.l	#0, %d0
379	beq	asm_dspi_rd_status
380
381	move.b	(%a3), %d1
382	rts
383
384asm_delay:
385	nop
386	subq.l	#1, %d1
387	bne	asm_delay
388	rts
389#endif			/* CONFIG_CF_SBF */
390
391	.text
392	. = 0x400
393	.globl	_start
394_start:
395#if !defined(CONFIG_CF_SBF)
396	nop
397	nop
398	move.w #0x2700,%sr		/* Mask off Interrupt */
399
400	/* Set vector base register at the beginning of the Flash */
401	move.l	#CONFIG_SYS_FLASH_BASE, %d0
402	movec	%d0, %VBR
403
404	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
405	movec	%d0, %RAMBAR1
406
407	/* initialize general use internal ram */
408	move.l #0, %d0
409	move.l #(ICACHE_STATUS), %a1	/* icache */
410	move.l #(DCACHE_STATUS), %a2	/* dcache */
411	move.l %d0, (%a1)
412	move.l %d0, (%a2)
413
414	/* invalidate and disable cache */
415	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
416	movec	%d0, %CACR		/* Invalidate cache */
417	move.l	#0, %d0
418	movec	%d0, %ACR0
419	movec	%d0, %ACR1
420	movec	%d0, %ACR2
421	movec	%d0, %ACR3
422
423	/* set stackpointer to end of internal ram to get some stackspace for
424	   the first c-code */
425	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
426	clr.l %sp@-
427#endif
428
429	move.l #__got_start, %a5	/* put relocation table address to a5 */
430
431	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
432	bsr board_init_f		/* run low-level board init code (from flash) */
433
434	/* board_init_f() does not return */
435
436/*------------------------------------------------------------------------------*/
437
438/*
439 * void relocate_code (addr_sp, gd, addr_moni)
440 *
441 * This "function" does not return, instead it continues in RAM
442 * after relocating the monitor code.
443 *
444 * r3 = dest
445 * r4 = src
446 * r5 = length in bytes
447 * r6 = cachelinesize
448 */
449	.globl	relocate_code
450relocate_code:
451	link.w %a6,#0
452	move.l 8(%a6), %sp		/* set new stack pointer */
453
454	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
455	move.l 16(%a6), %a0		/* Save copy of Destination Address */
456
457	move.l #CONFIG_SYS_MONITOR_BASE, %a1
458	move.l #__init_end, %a2
459	move.l %a0, %a3
460
461	/* copy the code to RAM */
4621:
463	move.l (%a1)+, (%a3)+
464	cmp.l  %a1,%a2
465	bgt.s	 1b
466
467/*
468 * We are done. Do not return, instead branch to second part of board
469 * initialization, now running from RAM.
470 */
471	move.l	%a0, %a1
472	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
473	jmp	(%a1)
474
475in_ram:
476
477clear_bss:
478	/*
479	 * Now clear BSS segment
480	 */
481	move.l	%a0, %a1
482	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
483	move.l	%a0, %d1
484	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
4856:
486	clr.l	(%a1)+
487	cmp.l	%a1,%d1
488	bgt.s	6b
489
490	/*
491	 * fix got table in RAM
492	 */
493	move.l	%a0, %a1
494	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
495	move.l	%a1,%a5			/* * fix got pointer register a5 */
496
497	move.l	%a0, %a2
498	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
499
5007:
501	move.l	(%a1),%d1
502	sub.l	#_start,%d1
503	add.l	%a0,%d1
504	move.l	%d1,(%a1)+
505	cmp.l	%a2, %a1
506	bne	7b
507
508	/* calculate relative jump to board_init_r in ram */
509	move.l %a0, %a1
510	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
511
512	/* set parameters for board_init_r */
513	move.l %a0,-(%sp)		/* dest_addr */
514	move.l %d0,-(%sp)		/* gd */
515	jsr	(%a1)
516
517/*------------------------------------------------------------------------------*/
518/* exception code */
519	.globl _fault
520_fault:
521	bra _fault
522	.globl	_exc_handler
523
524_exc_handler:
525	SAVE_ALL
526	movel	%sp,%sp@-
527	bsr exc_handler
528	addql	#4,%sp
529	RESTORE_ALL
530
531	.globl	_int_handler
532_int_handler:
533	SAVE_ALL
534	movel	%sp,%sp@-
535	bsr int_handler
536	addql	#4,%sp
537	RESTORE_ALL
538
539/*------------------------------------------------------------------------------*/
540
541	.globl	version_string
542version_string:
543	.ascii U_BOOT_VERSION
544	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
545	.ascii CONFIG_IDENT_STRING, "\0"
546	.align 4
547