1 /* 2 * 3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/processor.h> 27 28 #include <asm/immap.h> 29 #include <asm/io.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* 34 * Low Power Divider specifications 35 */ 36 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ 37 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ 38 39 #define CLOCK_PLL_FVCO_MAX 540000000 40 #define CLOCK_PLL_FVCO_MIN 300000000 41 42 #define CLOCK_PLL_FSYS_MAX 266666666 43 #define CLOCK_PLL_FSYS_MIN 100000000 44 #define MHZ 1000000 45 46 void clock_enter_limp(int lpdiv) 47 { 48 ccm_t *ccm = (ccm_t *)MMAP_CCM; 49 int i, j; 50 51 /* Check bounds of divider */ 52 if (lpdiv < CLOCK_LPD_MIN) 53 lpdiv = CLOCK_LPD_MIN; 54 if (lpdiv > CLOCK_LPD_MAX) 55 lpdiv = CLOCK_LPD_MAX; 56 57 /* Round divider down to nearest power of two */ 58 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; 59 60 /* Apply the divider to the system clock */ 61 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); 62 63 /* Enable Limp Mode */ 64 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 65 } 66 67 /* 68 * brief Exit Limp mode 69 * warning The PLL should be set and locked prior to exiting Limp mode 70 */ 71 void clock_exit_limp(void) 72 { 73 ccm_t *ccm = (ccm_t *)MMAP_CCM; 74 pll_t *pll = (pll_t *)MMAP_PLL; 75 76 /* Exit Limp mode */ 77 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 78 79 /* Wait for the PLL to lock */ 80 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) 81 ; 82 } 83 84 /* 85 * get_clocks() fills in gd->cpu_clock and gd->bus_clk 86 */ 87 int get_clocks(void) 88 { 89 90 ccm_t *ccm = (ccm_t *)MMAP_CCM; 91 pll_t *pll = (pll_t *)MMAP_PLL; 92 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; 93 int pllmult_pci[] = { 12, 6, 16, 8 }; 94 int vco = 0, bPci, temp, fbtemp, pcrvalue; 95 int *pPllmult = NULL; 96 u16 fbpll_mask; 97 98 #ifdef CONFIG_M54455EVB 99 u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3); 100 #endif 101 u8 bootmode; 102 103 /* To determine PCI is present or not */ 104 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || 105 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { 106 pPllmult = &pllmult_pci[0]; 107 fbpll_mask = 3; /* 11b */ 108 bPci = 1; 109 } else { 110 pPllmult = &pllmult_nopci[0]; 111 fbpll_mask = 7; /* 111b */ 112 #ifdef CONFIG_PCI 113 gd->pci_clk = 0; 114 #endif 115 bPci = 0; 116 } 117 118 #ifdef CONFIG_M54455EVB 119 bootmode = (in_8(cpld) & 0x03); 120 121 if (bootmode != 3) { 122 /* Temporary read from CCR- fixed fb issue, must be the same clock 123 as pci or input clock, causing cpld/fpga read inconsistancy */ 124 fbtemp = pPllmult[ccm->ccr & fbpll_mask]; 125 126 /* Break down into small pieces, code still in flex bus */ 127 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; 128 temp = fbtemp - 1; 129 pcrvalue |= PLL_PCR_OUTDIV3(temp); 130 131 out_be32(&pll->pcr, pcrvalue); 132 } 133 #endif 134 #ifdef CONFIG_M54451EVB 135 /* No external logic to read the bootmode, hard coded from built */ 136 #ifdef CONFIG_CF_SBF 137 bootmode = 3; 138 #else 139 bootmode = 2; 140 141 /* default value is 16 mul, set to 20 mul */ 142 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; 143 out_be32(&pll->pcr, pcrvalue); 144 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK) 145 ; 146 #endif 147 #endif 148 149 if (bootmode == 0) { 150 /* RCON mode */ 151 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; 152 153 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { 154 /* invaild range, re-set in PCR */ 155 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; 156 int i, j, bus; 157 158 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; 159 for (i = j; i < 0xFF; i++) { 160 vco = i * CONFIG_SYS_INPUT_CLKSRC; 161 if (vco >= CLOCK_PLL_FVCO_MIN) { 162 bus = vco / temp; 163 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) 164 continue; 165 else 166 break; 167 } 168 } 169 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF; 170 fbtemp = ((i - 1) << 8) | ((i - 1) << 12); 171 pcrvalue |= ((i << 24) | fbtemp); 172 173 out_be32(&pll->pcr, pcrvalue); 174 } 175 gd->vco_clk = vco; /* Vco clock */ 176 } else if (bootmode == 2) { 177 /* Normal mode */ 178 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; 179 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { 180 /* Default value */ 181 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); 182 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24; 183 out_be32(&pll->pcr, pcrvalue); 184 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; 185 } 186 gd->vco_clk = vco; /* Vco clock */ 187 } else if (bootmode == 3) { 188 /* serial mode */ 189 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; 190 gd->vco_clk = vco; /* Vco clock */ 191 } 192 193 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { 194 /* Limp mode */ 195 } else { 196 gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ 197 198 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; 199 gd->cpu_clk = vco / temp; /* cpu clock */ 200 201 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; 202 gd->bus_clk = vco / temp; /* bus clock */ 203 204 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; 205 gd->flb_clk = vco / temp; /* FlexBus clock */ 206 207 #ifdef CONFIG_PCI 208 if (bPci) { 209 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; 210 gd->pci_clk = vco / temp; /* PCI clock */ 211 } 212 #endif 213 } 214 215 #ifdef CONFIG_FSL_I2C 216 gd->i2c1_clk = gd->bus_clk; 217 #endif 218 219 return (0); 220 } 221