1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 #include <asm/immap.h> 31 #include <asm/processor.h> 32 #include <asm/rtc.h> 33 #include <asm/io.h> 34 #include <linux/compiler.h> 35 36 #if defined(CONFIG_CMD_NET) 37 #include <config.h> 38 #include <net.h> 39 #include <asm/fec.h> 40 #endif 41 42 /* 43 * Breath some life into the CPU... 44 * 45 * Set up the memory map, 46 * initialize a bunch of registers, 47 * initialize the UPM's 48 */ 49 void cpu_init_f(void) 50 { 51 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 52 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 53 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; 54 55 out_be32(&scm1->mpr, 0x77777777); 56 out_be32(&scm1->pacra, 0); 57 out_be32(&scm1->pacrb, 0); 58 out_be32(&scm1->pacrc, 0); 59 out_be32(&scm1->pacrd, 0); 60 out_be32(&scm1->pacre, 0); 61 out_be32(&scm1->pacrf, 0); 62 out_be32(&scm1->pacrg, 0); 63 64 /* FlexBus */ 65 out_8(&gpio->par_be, 66 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | 67 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); 68 out_8(&gpio->par_fbctl, 69 GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | 70 GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); 71 72 #if !defined(CONFIG_CF_SBF) 73 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) 74 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 75 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 76 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 77 #endif 78 #endif 79 80 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) 81 /* Latch chipselect */ 82 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 83 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 84 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 85 #endif 86 87 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) 88 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 89 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 90 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 91 #endif 92 93 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) 94 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 95 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 96 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 97 #endif 98 99 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) 100 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 101 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 102 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 103 #endif 104 105 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) 106 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 107 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 108 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 109 #endif 110 111 /* 112 * now the flash base address is no longer at 0 (Newer ColdFire family 113 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must 114 * also move to the new location. 115 */ 116 if (CONFIG_SYS_CS0_BASE != 0) 117 setvbr(CONFIG_SYS_CS0_BASE); 118 119 #ifdef CONFIG_FSL_I2C 120 out_be16(&gpio->par_feci2c, 121 GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); 122 #endif 123 124 icache_enable(); 125 } 126 127 /* 128 * initialize higher level parts of CPU like timers 129 */ 130 int cpu_init_r(void) 131 { 132 #ifdef CONFIG_MCFRTC 133 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); 134 rtcex_t *rtcex = (rtcex_t *)&rtc->extended; 135 136 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); 137 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); 138 #endif 139 140 return (0); 141 } 142 143 void uart_port_conf(int port) 144 { 145 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 146 147 /* Setup Ports: */ 148 switch (port) { 149 case 0: 150 clrbits_8(&gpio->par_uart, 151 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 152 setbits_8(&gpio->par_uart, 153 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 154 break; 155 case 1: 156 #ifdef CONFIG_SYS_UART1_PRI_GPIO 157 clrbits_8(&gpio->par_uart, 158 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 159 setbits_8(&gpio->par_uart, 160 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 161 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO) 162 clrbits_be16(&gpio->par_ssi, 163 ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK)); 164 setbits_be16(&gpio->par_ssi, 165 GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); 166 #endif 167 break; 168 case 2: 169 #if defined(CONFIG_SYS_UART2_ALT1_GPIO) 170 clrbits_8(&gpio->par_timer, 171 ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK)); 172 setbits_8(&gpio->par_timer, 173 GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); 174 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 175 clrbits_8(&gpio->par_timer, 176 ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK)); 177 setbits_8(&gpio->par_timer, 178 GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); 179 #endif 180 break; 181 } 182 } 183 184 #if defined(CONFIG_CMD_NET) 185 int fecpin_setclear(struct eth_device *dev, int setclear) 186 { 187 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 188 struct fec_info_s *info = (struct fec_info_s *)dev->priv; 189 190 if (setclear) { 191 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY 192 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 193 setbits_be16(&gpio->par_feci2c, 194 GPIO_PAR_FECI2C_MDC0_MDC0 | 195 GPIO_PAR_FECI2C_MDIO0_MDIO0); 196 else 197 setbits_be16(&gpio->par_feci2c, 198 GPIO_PAR_FECI2C_MDC1_MDC1 | 199 GPIO_PAR_FECI2C_MDIO1_MDIO1); 200 #else 201 setbits_be16(&gpio->par_feci2c, 202 GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); 203 #endif 204 205 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 206 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); 207 else 208 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); 209 } else { 210 clrbits_be16(&gpio->par_feci2c, 211 GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); 212 213 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 214 #ifdef CONFIG_SYS_FEC_FULL_MII 215 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); 216 #else 217 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK); 218 #endif 219 } else { 220 #ifdef CONFIG_SYS_FEC_FULL_MII 221 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII); 222 #else 223 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK); 224 #endif 225 } 226 } 227 return 0; 228 } 229 #endif 230 231 #ifdef CONFIG_CF_DSPI 232 void cfspi_port_conf(void) 233 { 234 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 235 236 out_8(&gpio->par_dspi, 237 GPIO_PAR_DSPI_SIN_SIN | 238 GPIO_PAR_DSPI_SOUT_SOUT | 239 GPIO_PAR_DSPI_SCK_SCK); 240 } 241 242 int cfspi_claim_bus(uint bus, uint cs) 243 { 244 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 245 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 246 247 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) 248 return -1; 249 250 /* Clear FIFO and resume transfer */ 251 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 252 253 switch (cs) { 254 case 0: 255 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 256 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 257 break; 258 case 1: 259 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); 260 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); 261 break; 262 case 2: 263 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); 264 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); 265 break; 266 case 3: 267 clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); 268 setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); 269 break; 270 case 5: 271 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); 272 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); 273 break; 274 } 275 276 return 0; 277 } 278 279 void cfspi_release_bus(uint bus, uint cs) 280 { 281 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 282 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 283 284 /* Clear FIFO */ 285 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 286 287 switch (cs) { 288 case 0: 289 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 290 break; 291 case 1: 292 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); 293 break; 294 case 2: 295 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); 296 break; 297 case 3: 298 clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); 299 break; 300 case 5: 301 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); 302 break; 303 } 304 } 305 #endif 306