1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 #include <asm/immap.h> 31 #include <asm/processor.h> 32 #include <asm/rtc.h> 33 34 #if defined(CONFIG_CMD_NET) 35 #include <config.h> 36 #include <net.h> 37 #include <asm/fec.h> 38 #endif 39 40 /* 41 * Breath some life into the CPU... 42 * 43 * Set up the memory map, 44 * initialize a bunch of registers, 45 * initialize the UPM's 46 */ 47 void cpu_init_f(void) 48 { 49 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 50 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 51 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 52 53 scm1->mpr = 0x77777777; 54 scm1->pacra = 0; 55 scm1->pacrb = 0; 56 scm1->pacrc = 0; 57 scm1->pacrd = 0; 58 scm1->pacre = 0; 59 scm1->pacrf = 0; 60 scm1->pacrg = 0; 61 62 /* FlexBus */ 63 gpio->par_be = 64 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | 65 GPIO_PAR_BE_BE0_BE0; 66 gpio->par_fbctl = 67 GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | 68 GPIO_PAR_FBCTL_TS_TS; 69 70 #if !defined(CONFIG_CF_SBF) 71 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) 72 fbcs->csar0 = CONFIG_SYS_CS0_BASE; 73 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; 74 fbcs->csmr0 = CONFIG_SYS_CS0_MASK; 75 #endif 76 #endif 77 78 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) 79 /* Latch chipselect */ 80 fbcs->csar1 = CONFIG_SYS_CS1_BASE; 81 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; 82 fbcs->csmr1 = CONFIG_SYS_CS1_MASK; 83 #endif 84 85 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) 86 fbcs->csar2 = CONFIG_SYS_CS2_BASE; 87 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; 88 fbcs->csmr2 = CONFIG_SYS_CS2_MASK; 89 #endif 90 91 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) 92 fbcs->csar3 = CONFIG_SYS_CS3_BASE; 93 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; 94 fbcs->csmr3 = CONFIG_SYS_CS3_MASK; 95 #endif 96 97 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) 98 fbcs->csar4 = CONFIG_SYS_CS4_BASE; 99 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; 100 fbcs->csmr4 = CONFIG_SYS_CS4_MASK; 101 #endif 102 103 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) 104 fbcs->csar5 = CONFIG_SYS_CS5_BASE; 105 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; 106 fbcs->csmr5 = CONFIG_SYS_CS5_MASK; 107 #endif 108 109 /* 110 * now the flash base address is no longer at 0 (Newer ColdFire family 111 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must 112 * also move to the new location. 113 */ 114 if (CONFIG_SYS_CS0_BASE != 0) 115 setvbr(CONFIG_SYS_CS0_BASE); 116 117 #ifdef CONFIG_FSL_I2C 118 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; 119 #endif 120 121 icache_enable(); 122 } 123 124 /* 125 * initialize higher level parts of CPU like timers 126 */ 127 int cpu_init_r(void) 128 { 129 #ifdef CONFIG_MCFRTC 130 volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); 131 volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; 132 133 rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; 134 rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; 135 #endif 136 137 return (0); 138 } 139 140 void uart_port_conf(int port) 141 { 142 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 143 144 /* Setup Ports: */ 145 switch (port) { 146 case 0: 147 gpio->par_uart &= 148 ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 149 gpio->par_uart |= 150 (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 151 break; 152 case 1: 153 #ifdef CONFIG_SYS_UART1_PRI_GPIO 154 gpio->par_uart &= 155 ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 156 gpio->par_uart |= 157 (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 158 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO) 159 gpio->par_ssi &= 160 (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK); 161 gpio->par_ssi |= 162 (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); 163 #endif 164 break; 165 case 2: 166 #if defined(CONFIG_SYS_UART2_ALT1_GPIO) 167 gpio->par_timer &= 168 (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK); 169 gpio->par_timer |= 170 (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); 171 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 172 gpio->par_timer &= 173 (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK); 174 gpio->par_timer |= 175 (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); 176 #endif 177 break; 178 } 179 } 180 181 #if defined(CONFIG_CMD_NET) 182 int fecpin_setclear(struct eth_device *dev, int setclear) 183 { 184 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 185 struct fec_info_s *info = (struct fec_info_s *)dev->priv; 186 187 if (setclear) { 188 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY 189 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 190 gpio->par_feci2c |= 191 (GPIO_PAR_FECI2C_MDC0_MDC0 | 192 GPIO_PAR_FECI2C_MDIO0_MDIO0); 193 else 194 gpio->par_feci2c |= 195 (GPIO_PAR_FECI2C_MDC1_MDC1 | 196 GPIO_PAR_FECI2C_MDIO1_MDIO1); 197 #else 198 gpio->par_feci2c |= 199 (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); 200 #endif 201 202 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 203 gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; 204 else 205 gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; 206 } else { 207 gpio->par_feci2c &= 208 ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); 209 210 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 211 #ifdef CONFIG_SYS_FEC_FULL_MII 212 gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII; 213 #else 214 gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK; 215 #endif 216 } else { 217 #ifdef CONFIG_SYS_FEC_FULL_MII 218 gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII; 219 #else 220 gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK; 221 #endif 222 } 223 } 224 return 0; 225 } 226 #endif 227 228 #ifdef CONFIG_CF_DSPI 229 void cfspi_port_conf(void) 230 { 231 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 232 233 gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | 234 GPIO_PAR_DSPI_SCK_SCK; 235 } 236 237 int cfspi_claim_bus(uint bus, uint cs) 238 { 239 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; 240 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 241 242 if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) 243 return -1; 244 245 /* Clear FIFO and resume transfer */ 246 dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); 247 248 switch (cs) { 249 case 0: 250 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; 251 gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; 252 break; 253 case 1: 254 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; 255 gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; 256 break; 257 case 2: 258 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; 259 gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; 260 break; 261 case 3: 262 gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK; 263 gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3; 264 break; 265 case 5: 266 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; 267 gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; 268 break; 269 } 270 271 return 0; 272 } 273 274 void cfspi_release_bus(uint bus, uint cs) 275 { 276 volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; 277 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 278 279 dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ 280 281 switch (cs) { 282 case 0: 283 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; 284 break; 285 case 1: 286 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; 287 break; 288 case 2: 289 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; 290 break; 291 case 3: 292 gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK; 293 break; 294 case 5: 295 gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; 296 break; 297 } 298 } 299 #endif 300