1 /* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <watchdog.h> 30 #include <asm/immap.h> 31 #include <asm/processor.h> 32 #include <asm/rtc.h> 33 #include <asm/io.h> 34 35 #if defined(CONFIG_CMD_NET) 36 #include <config.h> 37 #include <net.h> 38 #include <asm/fec.h> 39 #endif 40 41 /* 42 * Breath some life into the CPU... 43 * 44 * Set up the memory map, 45 * initialize a bunch of registers, 46 * initialize the UPM's 47 */ 48 void cpu_init_f(void) 49 { 50 scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 51 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 52 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 53 54 out_be32(&scm1->mpr, 0x77777777); 55 out_be32(&scm1->pacra, 0); 56 out_be32(&scm1->pacrb, 0); 57 out_be32(&scm1->pacrc, 0); 58 out_be32(&scm1->pacrd, 0); 59 out_be32(&scm1->pacre, 0); 60 out_be32(&scm1->pacrf, 0); 61 out_be32(&scm1->pacrg, 0); 62 63 /* FlexBus */ 64 out_8(&gpio->par_be, 65 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | 66 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); 67 out_8(&gpio->par_fbctl, 68 GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | 69 GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); 70 71 #if !defined(CONFIG_CF_SBF) 72 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) 73 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); 74 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); 75 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); 76 #endif 77 #endif 78 79 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) 80 /* Latch chipselect */ 81 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); 82 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); 83 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); 84 #endif 85 86 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) 87 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); 88 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); 89 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); 90 #endif 91 92 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) 93 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); 94 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); 95 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); 96 #endif 97 98 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) 99 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); 100 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); 101 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); 102 #endif 103 104 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) 105 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); 106 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); 107 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); 108 #endif 109 110 /* 111 * now the flash base address is no longer at 0 (Newer ColdFire family 112 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must 113 * also move to the new location. 114 */ 115 if (CONFIG_SYS_CS0_BASE != 0) 116 setvbr(CONFIG_SYS_CS0_BASE); 117 118 #ifdef CONFIG_FSL_I2C 119 out_be16(&gpio->par_feci2c, 120 GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); 121 #endif 122 123 icache_enable(); 124 } 125 126 /* 127 * initialize higher level parts of CPU like timers 128 */ 129 int cpu_init_r(void) 130 { 131 #ifdef CONFIG_MCFRTC 132 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); 133 rtcex_t *rtcex = (rtcex_t *)&rtc->extended; 134 135 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); 136 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); 137 #endif 138 139 return (0); 140 } 141 142 void uart_port_conf(int port) 143 { 144 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 145 146 /* Setup Ports: */ 147 switch (port) { 148 case 0: 149 clrbits_8(&gpio->par_uart, 150 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 151 setbits_8(&gpio->par_uart, 152 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); 153 break; 154 case 1: 155 #ifdef CONFIG_SYS_UART1_PRI_GPIO 156 clrbits_8(&gpio->par_uart, 157 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 158 setbits_8(&gpio->par_uart, 159 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); 160 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO) 161 clrbits_be16(&gpio->par_ssi, 162 ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK)); 163 setbits_be16(&gpio->par_ssi, 164 GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); 165 #endif 166 break; 167 case 2: 168 #if defined(CONFIG_SYS_UART2_ALT1_GPIO) 169 clrbits_8(&gpio->par_timer, 170 ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK)); 171 setbits_8(&gpio->par_timer, 172 GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); 173 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 174 clrbits_8(&gpio->par_timer, 175 ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK)); 176 setbits_8(&gpio->par_timer, 177 GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); 178 #endif 179 break; 180 } 181 } 182 183 #if defined(CONFIG_CMD_NET) 184 int fecpin_setclear(struct eth_device *dev, int setclear) 185 { 186 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 187 struct fec_info_s *info = (struct fec_info_s *)dev->priv; 188 189 if (setclear) { 190 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY 191 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 192 setbits_be16(&gpio->par_feci2c, 193 GPIO_PAR_FECI2C_MDC0_MDC0 | 194 GPIO_PAR_FECI2C_MDIO0_MDIO0); 195 else 196 setbits_be16(&gpio->par_feci2c, 197 GPIO_PAR_FECI2C_MDC1_MDC1 | 198 GPIO_PAR_FECI2C_MDIO1_MDIO1); 199 #else 200 setbits_be16(&gpio->par_feci2c, 201 GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); 202 #endif 203 204 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) 205 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); 206 else 207 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); 208 } else { 209 clrbits_be16(&gpio->par_feci2c, 210 GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); 211 212 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 213 #ifdef CONFIG_SYS_FEC_FULL_MII 214 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); 215 #else 216 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK); 217 #endif 218 } else { 219 #ifdef CONFIG_SYS_FEC_FULL_MII 220 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII); 221 #else 222 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK); 223 #endif 224 } 225 } 226 return 0; 227 } 228 #endif 229 230 #ifdef CONFIG_CF_DSPI 231 void cfspi_port_conf(void) 232 { 233 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 234 235 out_8(&gpio->par_dspi, 236 GPIO_PAR_DSPI_SIN_SIN | 237 GPIO_PAR_DSPI_SOUT_SOUT | 238 GPIO_PAR_DSPI_SCK_SCK); 239 } 240 241 int cfspi_claim_bus(uint bus, uint cs) 242 { 243 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 244 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 245 246 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) 247 return -1; 248 249 /* Clear FIFO and resume transfer */ 250 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 251 252 switch (cs) { 253 case 0: 254 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 255 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 256 break; 257 case 1: 258 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); 259 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); 260 break; 261 case 2: 262 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); 263 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); 264 break; 265 case 3: 266 clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); 267 setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); 268 break; 269 case 5: 270 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); 271 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); 272 break; 273 } 274 275 return 0; 276 } 277 278 void cfspi_release_bus(uint bus, uint cs) 279 { 280 dspi_t *dspi = (dspi_t *) MMAP_DSPI; 281 gpio_t *gpio = (gpio_t *) MMAP_GPIO; 282 283 /* Clear FIFO */ 284 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); 285 286 switch (cs) { 287 case 0: 288 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); 289 break; 290 case 1: 291 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); 292 break; 293 case 2: 294 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); 295 break; 296 case 3: 297 clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); 298 break; 299 case 5: 300 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); 301 break; 302 } 303 } 304 #endif 305